Issued Patents All Time
Showing 1,451–1,475 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9024438 | Self-aligning conductive bump structure and method of making the same | Cheng-Lin Huang, I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu-Wei Lu +2 more | 2015-05-05 |
| 9024431 | Semiconductor die contact structure and method | Chung-Shi Liu | 2015-05-05 |
| 9021682 | Apparatus for stud bump formation | Chien Ling Hwang, Yeong-Jyh Lin, Yi-Li Hsiao, Ming-Da Cheng, Tsai-Tsung Tsai +2 more | 2015-05-05 |
| 9018757 | Mechanisms for forming bump structures over wide metal pad | Chung-Hao Tsai, Chuei-Tang Wang | 2015-04-28 |
| 9010617 | Solder joint reflow process for reducing packaging failure rate | Wen-Yao Chang, Chien Rhone Wang, Kewei Zuo, Chung-Shi Liu | 2015-04-21 |
| 9013038 | Semiconductor device with post-passivation interconnect structure and method of forming the same | Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii | 2015-04-21 |
| 9006097 | Cu pillar bump with electrolytic metal sidewall protection | Wen-Hsiung Lu, Ming-Da Cheng, Chih-Wei Lin, Jacky Chang, Chung-Shi Liu | 2015-04-14 |
| 8999179 | Conductive vias in a substrate | Der-Chyang Yeh | 2015-04-07 |
| 9001308 | Pattern generator for a lithography system | Tien-I Bao, Chih Wei Lu, Jaw-Jung Shin, Shy-Jay Lin, Burn Jeng Lin | 2015-04-07 |
| 8994188 | Interconnect structures for substrate | Wen-Chih Chiou, Shin-Puu Jeng, Tsang-Jiuh Wu | 2015-03-31 |
| 8993432 | Test structure and method of testing electrical characteristics of through vias | Shang-Yun Hou, Wei-Cheng Wu, Hsien-Pin Hu, Jung Cheng Ko, Shin-Puu Jeng +1 more | 2015-03-31 |
| 8993380 | Structure and method for 3D IC package | Shang-Yun Hou, Der-Chyang Yeh, Shin-Puu Jeng | 2015-03-31 |
| 8987915 | Semiconductor structure and manufacturing method thereof | Mirng-Ji Lii, Chung-Shi Liu, Chang-Chia Huang, Chih-Wei Lin, Ming-Da Cheng | 2015-03-24 |
| 8987085 | Methods for improving uniformity of cap layers | Ming-Shih Yeh, Chih-Hsien Lin, Yung-Cheng Lu, Hui-Lin Chang | 2015-03-24 |
| 8981576 | Structure and method for bump to landing trace ratio | Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yen-Liang Lin | 2015-03-17 |
| 8963334 | Die-to-die gap control for semiconductor structure and method | Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih, Ying-Da Wang, Li-Chung Kuo +2 more | 2015-02-24 |
| 8957477 | Germanium FinFETs having dielectric punch-through stoppers | Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh | 2015-02-17 |
| 8952506 | Through silicon via structure | Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai | 2015-02-10 |
| 8946742 | Semiconductor package with through silicon vias | Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang | 2015-02-03 |
| 8941239 | Copper interconnect structure and method for forming the same | Shau-Lin Shue, Hsiang-Huan Lee, Ching-Fu Yeh | 2015-01-27 |
| 8936730 | Methods for forming apparatus for stud bump formation | Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Chung-Shi Liu, Mirng-Ji Lii +1 more | 2015-01-20 |
| 8933551 | 3D-packages and methods for forming the same | Chin-Chuan Chang, Jing-Cheng Lin | 2015-01-13 |
| 8927412 | Multi-chip package and method of formation | Jing-Cheng Lin, Jui-Pin Hung, Der-Chyang Yeh | 2015-01-06 |
| 8928117 | Multi-chip package structure and method of forming same | Jui-Pin Hung, Jing-Cheng Lin, Der-Chyang Yeh | 2015-01-06 |
| 8916956 | Multiple die packaging interposer structure and method | Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu | 2014-12-23 |