Issued Patents All Time
Showing 1,401–1,425 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9230959 | FinFETs having dielectric punch-through stoppers | Cheng-Hung Chang, Chen-Nan Yeh | 2016-01-05 |
| 9230902 | Interconnect structure for wafer level package | Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng | 2016-01-05 |
| 9230932 | Interconnect crack arrestor structure and methods | Da-Yuan Shih | 2016-01-05 |
| 9224606 | Method of fabricating semiconductor device isolation structure | Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen | 2015-12-29 |
| 9219030 | Package on package structures and methods for forming the same | Mirng-Ji Lii, Chung-Shi Liu, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng | 2015-12-22 |
| 9216469 | Indirect printing bumping method for solder ball deposition | Yi-Li Hsiao, Da-Yuan Shih, Chih-Hang Tung | 2015-12-22 |
| 9214428 | Self-aligned protection layer for copper post structure | Chung-Shi Liu | 2015-12-15 |
| 9214613 | Method of forming light-generating device including reflective layer | Ding-Yuan Chen, Chia-Lin Yu, Wen-Chih Chiou | 2015-12-15 |
| 9209157 | Formation of through via before contact processing | Wen-Chih Chiou, Weng-Jin Wu | 2015-12-08 |
| 9177843 | Preventing contamination in integrated circuit manufacturing lines | Chien-Ming Sung, Simon Wang, Jia-Ren Chen, Henry Lo, Jean Wang +1 more | 2015-11-03 |
| 9171790 | Package on package devices and methods of packaging semiconductor dies | Yung Ching Chen, Chien-Hsun Lee, Jiun Yi Wu, Mirng-Ji Lii, Ming-Da Cheng | 2015-10-27 |
| 9171815 | Method of forming package systems having interposers | Yung-Chi Lin, Jing-Cheng Lin | 2015-10-27 |
| 9165875 | Low profile interposer with stud structure | Mirng-Ji Lii, Hao-Yi Tsai, Kai-Chiang Wu | 2015-10-20 |
| 9165885 | Staggered via redistribution layer (RDL) for a package and a method for forming the same | Chung-Shi Liu, Hung-Jui Kuo | 2015-10-20 |
| 9159673 | Forming interconnect structures using pre-ink-printed sheets | Jung Cheng Ko, Chi-Chun Hsieh, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng | 2015-10-13 |
| 9153506 | System and method for through silicon via yield | Chien Rhone Wang, Kewei Zuo, Jing-Cheng Lin, Yen-Hsin Liu | 2015-10-06 |
| 9153540 | Semiconductor die connection system and method | Ming-Fa Chen, Sen-Bor Jan | 2015-10-06 |
| 9142509 | Copper interconnect structure and method for forming the same | Shau-Lin Shue, Hsiang-Huan Lee, Ching-Fu Yeh | 2015-09-22 |
| 9136143 | Thermally enhanced structure for multi-chip device | Chih-Hang Tung, Tung-Liang Shao | 2015-09-15 |
| 9129944 | Fan-out package structure and methods for forming the same | Der-Chyang Yeh | 2015-09-08 |
| 9130115 | Light-emitting diode with textured substrate | Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu, Hung-Ta Lin | 2015-09-08 |
| 9129968 | Schemes for forming barrier layers for copper in interconnect structures | Hai-Ching Chen, Tien-I Bao | 2015-09-08 |
| 9128123 | Interposer test structures and methods | Tzuan-Horng Liu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou +1 more | 2015-09-08 |
| 9123763 | Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material | Chung-Shi Liu, Mirng-Ji Lii, Ming-Da Cheng, Chih-Wei Lin | 2015-09-01 |
| 9123553 | Method and system for bonding 3D semiconductor device | Chung-Shi Liu, Yuh-Jier Mii, Yuan-Chen Sun | 2015-09-01 |