Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12354634 | Transistorless memory cell | Katherine H. Chiang, Chung-Te Lin, Min Cao, Sheng-Chih Lai | 2025-07-08 |
| 11990169 | Transistorless memory cell | Katherine H. Chiang, Chung-Te Lin, Min Cao, Sheng-Chih Lai | 2024-05-21 |
| 11094361 | Transistorless memory cell | Katherine H. Chiang, Chung-Te Lin, Min Cao, Sheng-Chih Lai | 2021-08-17 |
| 10361152 | Semiconductor structure having an air-gap region and a method of manufacturing the same | Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu +1 more | 2019-07-23 |
| 9496217 | Method and apparatus of forming a via | Hsin-Yi Tsai, Chih-Hao Chen, Ming-Chung Liang, Chii-Ping Chen, Lai Chien Wen | 2016-11-15 |
| 9123553 | Method and system for bonding 3D semiconductor device | Chung-Shi Liu, Chen-Hua Yu, Yuan-Chen Sun | 2015-09-01 |
| 8999839 | Semiconductor structure having an air-gap region and a method of manufacturing the same | Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu +1 more | 2015-04-07 |
| 8975749 | Method of making a semiconductor device including barrier layers for copper interconnect | Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang +2 more | 2015-03-10 |
| 8680597 | Method and apparatus for improving gate contact | Harry-Hak-Lay Chuang, Chih-Yang Yeh, Bao-Ru Young | 2014-03-25 |
| 8653664 | Barrier layers for copper interconnect | Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang +2 more | 2014-02-18 |
| 8524570 | Method and apparatus for improving gate contact | Harry-Hak-Lay Chuang, Chih-Yang Yeh, Bao-Ru Young | 2013-09-03 |
| 8456009 | Semiconductor structure having an air-gap region and a method of manufacturing the same | Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu +1 more | 2013-06-04 |
| 8304906 | Partial air gap formation for providing interconnect isolation in integrated circuits | Cheng-Lin Huang, Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen | 2012-11-06 |
| 8294212 | Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed | Ping-Wei Wang, Chang-Ta Yang | 2012-10-23 |
| 8217469 | Contact implement structure for high density design | Yung-Chin Hou, Kuo-Tung Sung, Li-Chun Tien | 2012-07-10 |
| 8115500 | Accurate capacitance measurement for ultra large scale integrated circuits | Yih-Yuh Doong, Keh-Jeng Chang, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang | 2012-02-14 |
| 8048717 | Method and system for bonding 3D semiconductor devices | Chung-Shi Liu, Chen-Hua Yu, Yuan-Chen Sun | 2011-11-01 |
| 7880494 | Accurate capacitance measurement for ultra large scale integrated circuits | Yih-Yuh Doong, Keh-Jeng Chang, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang | 2011-02-01 |
| 7826252 | Read-preferred SRAM cell design | Ping-Wei Wang, Hung-Jen Liao | 2010-11-02 |
| 7772868 | Accurate capacitance measurement for ultra large scale integrated circuits | Yih-Yuh Doong, Keh-Jeng Chang, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang | 2010-08-10 |
| 7436696 | Read-preferred SRAM cell design | Ping-Wei Wang, Hung-Jen Liao | 2008-10-14 |
| 7359272 | Circuit and method for an SRAM with reduced power consumption | Ping-Wei Wang | 2008-04-15 |
| 6114747 | Process design for wafer edge in VLSI | Zin-Chein Wei | 2000-09-05 |
| 5966628 | Process design for wafer edge in vlsi | Zin-Chein Wei | 1999-10-12 |
| 5900644 | Test site and a method of monitoring via etch depths for semiconductor devices | Shu-Lan Ying, Yuan-Chang Huang, Jue-Jye Chen | 1999-05-04 |