Issued Patents All Time
Showing 1–25 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431192 | Semiconductor device | Nikhil Puri, Venkateswara Reddy Konudula, Teja Masina, Yen-Huei Chen, Hidehiro Fujiwara | 2025-09-30 |
| 12412621 | Semiconductor device including distributed write driving arrangement | Hidehiro Fujiwara, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2025-09-09 |
| 12408316 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen | 2025-09-02 |
| 12400723 | Latch type sense amplifier for testing | Hua-Hsin Yu, Hau-Tai Shieh, Cheng Hung Lee | 2025-08-26 |
| 12380946 | Memory computation method | Yen-Huei Chen, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang | 2025-08-05 |
| 12347483 | Arrangements of memory devices and methods of operating the memory devices | Chien-Yuan Chen, Hau-Tai Shieh, Cheng Hung Lee | 2025-07-01 |
| 12346143 | Voltage regulator with power rail tracking | Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu +2 more | 2025-07-01 |
| 12322438 | Latch circuit formed by modified memory cells | Hua-Hsin Yu, Cheng Hung Lee, Hau-Tai Shieh | 2025-06-03 |
| 12308303 | Integrated circuit die with memory macro including through-silicon via and method of forming the same | Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Jonathan Tsung-Yung Chang +2 more | 2025-05-20 |
| 12300312 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Chiting Cheng, Tsung-Yung Chang | 2025-05-13 |
| 12300605 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hau-Tai Shieh, Kao-Cheng Lin, Wei Min Chan | 2025-05-13 |
| 12254919 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh | 2025-03-18 |
| 12249391 | Latch type sense amplifier | Hua-Hsin Yu, Cheng Hung Lee, Hau-Tai Shieh | 2025-03-11 |
| 12245412 | SRAM cell word line structure with reduced RC effects | Hidehiro Fujiwara, Wei Min Chan, Chih-Yu Lin, Yen-Huei Chen | 2025-03-04 |
| 12205664 | Memory circuit and method of operating same | Hua-Hsin Yu, Hau-Tai Shieh, Cheng Hung Lee | 2025-01-21 |
| 12183428 | Memory circuit and method of operating the same | Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Fu-An Wu, He-Zhou WAN +1 more | 2024-12-31 |
| 12136460 | Floating data line circuit and method | Manish Arora, Yen-Huei Chen, Nikhil Puri, Yu-Hao Hsu | 2024-11-05 |
| 12119052 | Low voltage memory device | Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Jonathan Tsung-Yung Chang | 2024-10-15 |
| 12074156 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Sahil Preet Singh, Chih-Yu Lin, Hsien-Yu Pan, Yen-Huei Chen | 2024-08-27 |
| 12072750 | Power management circuit, system-on-chip device, and method of power management | Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Cheng Hung Lee | 2024-08-27 |
| 12029023 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen | 2024-07-02 |
| 11989046 | Voltage regulator with power rail tracking | Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu +2 more | 2024-05-21 |
| 11948627 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen | 2024-04-02 |
| 11929109 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh | 2024-03-12 |
| 11915743 | Latch circuit | Hua-Hsin Yu, Cheng Hung Lee, Hau-Tai Shieh | 2024-02-27 |