Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12308303 | Integrated circuit die with memory macro including through-silicon via and method of forming the same | Hidehiro Fujiwara, Tze-Chiang Huang, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2025-05-20 |
| 11854943 | Memory macro including through-silicon via | Hidehiro Fujiwara, Tze-Chiang Huang, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2023-12-26 |
| 11723195 | Semiconductor device having an inter-layer via (ILV), and method of making same | Tsung-Hsien Huang, Hung-Jen Liao, Cheng Hung Lee | 2023-08-08 |
| 11562946 | Memory macro including through-silicon via | Hidehiro Fujiwara, Tze-Chiang Huang, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2023-01-24 |
| 11138359 | Method of fabricating a semiconductor device | Annie-Li-Keow Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Vineet Agrawal +2 more | 2021-10-05 |
| 11024634 | Semiconductor device having an inter-layer via (ILV), and method of making same | Tsung-Hsien Huang, Cheng Hung Lee, Hung-Jen Liao | 2021-06-01 |
| 10866281 | System and method to diagnose integrated circuit | Wei-Pin Changchien, Pei-Ying Lin, Hsin-Wu Hsu | 2020-12-15 |
| 10762269 | Method of fabricating a semiconductor device | Annie-Li-Keow Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Vineet Agrawal +2 more | 2020-09-01 |
| 10339248 | Modified design rules to improve device performance | Annie-Li-Keow Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Vineet Agrawal +2 more | 2019-07-02 |
| 10267853 | System and method to diagnose integrated circuit | Wei-Pin Changchien, Pei-Ying Lin, Hsin-Wu Hsu | 2019-04-23 |
| 10170487 | Device having an inter-layer via (ILV), and method of making same | Tsung-Hsien Huang, Cheng Hung Lee, Hung-Jen Liao | 2019-01-01 |
| 10049706 | Memory and method of operating the same | Jung-Ping Yang, Chih-Chieh Chiu, Chia-En Huang, Cheng Hung Lee | 2018-08-14 |
| 10001801 | Voltage providing circuit | I-Han Huang, Chia-En Huang, Chih-Chieh Chiu, Fu-An Wu, Chun-Jiun Dai +2 more | 2018-06-19 |
| 9852249 | Modified design rules to improve device performance | Annie-Li-Keow Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Vineet Agrawal +2 more | 2017-12-26 |
| 9685226 | Tracking signals in memory write or read operation | Chih-Chieh Chiu | 2017-06-20 |
| 9679619 | Sense amplifier with current regulating circuit | Chi-Kai Hsieh, Cheng Hung Lee | 2017-06-13 |
| 9589885 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Chien-Chi TIEN, Ching-Wei Wu, Jui-Che Tsai +1 more | 2017-03-07 |
| 9484350 | Semiconductor device having an inter-layer via (ILV), and method of making same | Tsung-Hsien Huang, Cheng Hung Lee, Hung-Jen Liao | 2016-11-01 |
| 9324453 | Memory unit and method of testing the same | Wei-jer Hsieh, Chiting Cheng, Yangsyu Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-04-26 |
| 9287276 | Memory cell array | Shi-Wei Chang, Chien-Chi TIEN, Li-Chun Tien, Kuo-Hua Pan, Jhon Jhy Liaw | 2016-03-15 |
| 9275181 | Cell design | Chia-En Huang, Yi-Hung Tsai, Chih-Chieh Chiu, Hsiao-Lan Yang, I-Han Huang +4 more | 2016-03-01 |
| 9153302 | Memory and method of operating the same | Jung-Ping Yang, Chih-Chieh Chiu, Chia-En Huang, Cheng Hung Lee | 2015-10-06 |
| 9142274 | Tracking for write operations of memory devices | — | 2015-09-22 |
| 9129956 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Chien-Chi TIEN, Ching-Wei Wu, Jui-Che Tsai +1 more | 2015-09-08 |
| 9104214 | Voltage providing circuit | I-Han Huang, Chia-En Huang, Chih-Chieh Chiu, Fu-An Wu, Chun-Jiun Dai +2 more | 2015-08-11 |