Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12171092 | Layout of static random access memory periphery circuit | Yangsyu Lin, Chi-Lung Lee, Chiting Cheng | 2024-12-17 |
| 12136466 | Header layout design including backside power rail | Haruki Mori, Chia-En Huang, Hidehiro Fujiwara, Yen-Huei Chen, Feng-Lun CHEN | 2024-11-05 |
| 11995388 | Integrated circuit and method of forming same | Po-Sheng Wang, Chao-Yuan Cheng, Yangsyu Lin | 2024-05-28 |
| 11855619 | Power switch circuit, IC structure of power switch circuit, and method of forming IC structure | TZUNG-YO HUNG, Pin-Dai Sue, Ting-Wei Chiang | 2023-12-26 |
| 11856747 | Layout of static random access memory periphery circuit | Yangsyu Lin, Chi-Lung Lee, Chiting Cheng | 2023-12-26 |
| 11715501 | Header layout design including backside power rail | Haruki Mori, Chia-En Huang, Hidehiro Fujiwara, Yen-Huei Chen, Feng-Lun CHEN | 2023-08-01 |
| 11651133 | Integrated circuit and method of forming same | Po-Sheng Wang, Chao-Yuan Cheng, Yangsyu Lin | 2023-05-16 |
| 11398257 | Header layout design including backside power rail | Haruki Mori, Chia-En Huang, Hidehiro Fujiwara, Yen-Huei Chen, Feng-Lun CHEN | 2022-07-26 |
| 11342340 | Layout of static random access memory periphery circuit | Yangsyu Lin, Chi-Lung Lee, Chiting Cheng | 2022-05-24 |
| 11238905 | Sense amplifier layout for FinFET technology | Yen-Huei Chen, Kao-Cheng Lin, Jung-Hsuan Chen | 2022-02-01 |
| 10818677 | Layout of static random access memory periphery circuit | Yangsyu Lin, Chi-Lung Lee, Chiting Cheng | 2020-10-27 |
| 10636458 | Sense amplifier layout for FinFET technology | Yen-Huei Chen, Kao-Cheng Lin, Jung-Hsuan Chen | 2020-04-28 |
| 10032490 | Sense amplifier layout for FinFET technology | Yen-Huei Chen, Kao-Cheng Lin, Jung-Hsuan Chen | 2018-07-24 |
| 9589885 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Ching-Wei Wu, Jui-Che Tsai, Hong-Chen Cheng +1 more | 2017-03-07 |
| 9466493 | Sense amplifier layout for FinFET technology | Yen-Huei Chen, Kao-Cheng Lin, Jung-Hsuan Chen | 2016-10-11 |
| 9287276 | Memory cell array | Shi-Wei Chang, Hong-Chen Cheng, Li-Chun Tien, Kuo-Hua Pan, Jhon Jhy Liaw | 2016-03-15 |
| 9129956 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Ching-Wei Wu, Jui-Che Tsai, Hong-Chen Cheng +1 more | 2015-09-08 |