Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406704 | Multi-stage bit line pre-charge | Wei-Cheng Wu, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan +1 more | 2025-09-02 |
| 12382725 | Variable-sized active regions for a semiconductor device and methods of making same | Ru-Yu WANG, You-Cheng Xiao, Pin-Dai Sue, Ting-Wei Chiang | 2025-08-05 |
| 12334178 | Integrated circuit, system and method of forming the same | Yen Lin CHUNG, Wei Min Chan, Yen-Huei Chen | 2025-06-17 |
| 12300605 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Wei Min Chan | 2025-05-13 |
| 12205634 | Electronic circuits, memory devices, and methods for operating an electronic circuit | Wei-Cheng Wu, Pei-Yuan Li, Chien Hui HUANG, Yung-Ning TU | 2025-01-21 |
| 12183417 | Memory device and manufacturing method of the same | Po-Sheng Wang, Yangsyu Lin, Yen-Huei Chen, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2024-12-31 |
| 12176026 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen | 2024-12-24 |
| 11961554 | Shared power footer circuit | Hidehiro Fujiwara, Wei Min Chan, Yen-Huei Chen | 2024-04-16 |
| 11923034 | Header circuit placement in memory device | Po-Sheng Wang, Yangsyu Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2024-03-05 |
| 11854970 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Wei Min Chan | 2023-12-26 |
| 11749321 | Multi-stage bit line pre-charge | Wei-Cheng Wu, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan +1 more | 2023-09-05 |
| 11734142 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr. +5 more | 2023-08-22 |
| 11676660 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen | 2023-06-13 |
| 11538507 | Header circuit placement in memory device | Po-Sheng Wang, Yangsyu Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2022-12-27 |
| 11450605 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Wei Min Chan | 2022-09-20 |
| 11264088 | Semiconductor memory with respective power voltages for memory cells | Wei-Cheng Wu, Chih-Yu Lin, Wei Min Chan, Yen-Huei Chen | 2022-03-01 |
| 11256588 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr. +5 more | 2022-02-22 |
| 11238905 | Sense amplifier layout for FinFET technology | Yen-Huei Chen, Chien-Chi TIEN, Jung-Hsuan Chen | 2022-02-01 |
| 11205475 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen | 2021-12-21 |
| 11100964 | Multi-stage bit line pre-charge | Wei-Cheng Wu, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan +1 more | 2021-08-24 |
| 10783954 | Semiconductor memory with respective power voltages for memory cells | Wei-Cheng Wu, Chih-Yu Lin, Wei Min Chan, Yen-Huei Chen | 2020-09-22 |
| 10705934 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr. +5 more | 2020-07-07 |
| 10651114 | Apparatus and method of three dimensional conductive lines | Chih-Yu Lin, Li-Wen Wang, Yen-Huei Chen | 2020-05-12 |
| 10650882 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen | 2020-05-12 |
| 10636458 | Sense amplifier layout for FinFET technology | Yen-Huei Chen, Chien-Chi TIEN, Jung-Hsuan Chen | 2020-04-28 |