Issued Patents All Time
Showing 1–25 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400690 | Global boosting circuit | Ishan Khera | 2025-08-26 |
| 12379740 | Technique to mitigate clock generation failure at high input clock slew | Jaspal Singh Shah | 2025-08-05 |
| 12374375 | Tracking circuitry and memory devices including the same | Sanjeev Kumar Jain | 2025-07-29 |
| 12374386 | Variable voltage bit line precharge | Adrian Earle | 2025-07-29 |
| 12361991 | Far end driver for memory clock | — | 2025-07-15 |
| 12340869 | Low power wake up for memory | Sanjeev Kumar Jain | 2025-06-24 |
| 12327586 | Bit line pre-charge circuit for power management modes in multi bank SRAM | Sanjeev Kumar Jain, Ruchin Jain, Arun Achyuthan | 2025-06-10 |
| 12322474 | Memory device, read clock generation circuit, and method for controlling read operation in memory device | Sanjeev Kumar Jain | 2025-06-03 |
| 12315552 | Word line delay interlock circuit for write operation | Sergiy Romanovskyy | 2025-05-27 |
| 12277991 | Memory device with reset voltage control | Ali Taghvaei | 2025-04-15 |
| 12272427 | Semiconductor device including first and second clock generators | Jaspal Singh Shah, Sahil Preet Singh | 2025-04-08 |
| 12243602 | Method, device, and circuit for high-speed memories | Jaspal Singh Shah | 2025-03-04 |
| 12217792 | Memory circuit and method of operating same | Sahil Preet Singh | 2025-02-04 |
| 12190944 | Memory device with signal edge sharpener circuitry | — | 2025-01-07 |
| 12165739 | Systems and methods for controlling power management operations in a memory device | Sanjeev Kumar Jain, Sahil Preet Singh | 2024-12-10 |
| 12136454 | Memory device having a comparator circuit | Jaspal Singh Shah | 2024-11-05 |
| 12131770 | Word line booster circuit and method | — | 2024-10-29 |
| 12073877 | Robust circuit for negative bit line generation in SRAM cells | Sanjeev Kumar Jain | 2024-08-27 |
| 12033719 | Semiconductor device and method of operating the same | Shiba Mohanty | 2024-07-09 |
| 12009055 | Far end driver for memory clock | — | 2024-06-11 |
| 11935589 | Bit line pre-charge circuit for power management modes in multi bank SRAM | Sanjeev Kumar Jain, Ruchin Jain, Arun Achyuthan | 2024-03-19 |
| 11929113 | Variable voltage bit line precharge | Adrian Earle | 2024-03-12 |
| 11929110 | Memory circuit and method of operating same | Sanjeev Kumar Jain, Ishan Khera | 2024-03-12 |
| 11922998 | Memory device with global and local latches | Sahil Preet Singh | 2024-03-05 |
| 11894086 | Method, device, and circuit for high-speed memories | Jaspal Singh Shah | 2024-02-06 |