Issued Patents All Time
Showing 26–50 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854587 | Low power wake up for memory | Sanjeev Kumar Jain | 2023-12-26 |
| 11763863 | Systems and methods for controlling power management operations in a memory device | Sanjeev Kumar Jain, Sahil Preet Singh | 2023-09-19 |
| 11734142 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr., Hao-I Yang +5 more | 2023-08-22 |
| 11721380 | Word-line driver and method of operating a word-line driver | Ali Taghvaei | 2023-08-08 |
| 11705183 | Word line booster circuit and method | — | 2023-07-18 |
| 11626158 | Bit line pre-charge circuit for power management modes in multi bank SRAM | Sanjeev Kumar Jain, Ruchin Jain, Arun Achyuthan | 2023-04-11 |
| 11521673 | Variable voltage bit line precharge | Adrian Earle | 2022-12-06 |
| 11398271 | Memory device having a comparator circuit | Jaspal Singh Shah | 2022-07-26 |
| 11361818 | Memory device with global and local latches | Sahil Preet Singh | 2022-06-14 |
| 11309000 | Systems and methods for controlling power management operations in a memory device | Sanjeev Kumar Jain, Sahil Preet Singh | 2022-04-19 |
| 11295791 | SRAM with local bit line, input/output circuit, and global bit line | Ali Taghvaei | 2022-04-05 |
| 11256588 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr., Hao-I Yang +5 more | 2022-02-22 |
| 11031063 | Word-line driver and method of operating a word-line driver | Ali Taghvaei | 2021-06-08 |
| 10984854 | Memory device with signal edge sharpener circuitry | — | 2021-04-20 |
| 10923184 | Dual rail SRAM device | Sanjeev Kumar Jain | 2021-02-16 |
| 10923182 | Fixed-level charge sharing type LCV for memory compiler | Adrian Earle | 2021-02-16 |
| 10878867 | Memory cell distance tracking circuits and methods | Hyunsung Hong | 2020-12-29 |
| 10789994 | Memory architecture having first and second voltages | Cormac Michael O'Connell | 2020-09-29 |
| 10783938 | SRAM with local bit line, input/output circuit, and global bit line | Ali Taghvaei | 2020-09-22 |
| 10770122 | Memory input hold time adjustment | Sanjeev Kumar Jain, Marcin Dziok | 2020-09-08 |
| 10705934 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr., Hao-I Yang +5 more | 2020-07-07 |
| 10699766 | Word-line driver and method of operating a word-line driver | Ali Taghvaei | 2020-06-30 |
| 10522202 | Memory device and compensation method therein | Sanjeev Kumar Jain | 2019-12-31 |
| 10515690 | Memory architecture and method of access thereto | Cormac Michael O'Connell | 2019-12-24 |
| 10475502 | Word-line driver and method of operating a word-line driver | Ali Taghvaei | 2019-11-12 |