Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11734142 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Hao-I Yang +5 more | 2023-08-22 |
| 11256588 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Hao-I Yang +5 more | 2022-02-22 |
| 10705934 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Hao-I Yang +5 more | 2020-07-07 |
| 8502564 | Adjustable Schmitt trigger | — | 2013-08-06 |
| 8437214 | Memory cell employing reduced voltage | Hugh Mair, Theodore W. Houston, Michael Patrick Clinton | 2013-05-07 |
| 8248867 | Memory cell employing reduced voltage | Hugh Mair, Theodore W. Houston, Michael Patrick Clinton | 2012-08-21 |
| 7864600 | Memory cell employing reduced voltage | Hugh Mair, Theodore W. Houston, Michael Patrick Clinton | 2011-01-04 |
| 7660150 | Memory cell having improved write stability | Hugh Mair | 2010-02-09 |
| 6737888 | Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement | George McNeil Lattimore, Jose Angel Paredes, Gus Yeung | 2004-05-18 |
| 6667637 | Dynamic logic circuit with beta controllable noise margin | — | 2003-12-23 |
| 6532544 | High gain local clock buffer for a mesh clock distribution utilizing a gain enhanced split driver clock buffer | Robert P. Masleid | 2003-03-11 |
| 6445236 | Master-slave flip-flop circuit with embedded hold function and method for holding data in a master-slave flip-flop circuit | Jennifer Michelle Bernard, Christopher McCall Durham, Peter Juergen Klim | 2002-09-03 |
| 6240536 | Scanable latch circuit and method for providing a scan output from a latch circuit | Johnny LeBlanc | 2001-05-29 |
| 6157216 | Circuit driver on SOI for merged logic and memory circuits | George McNeil Lattimore, Binta M. Patel, Gus Yeung | 2000-12-05 |
| 6144325 | Register file array having a two-bit to four-bit encoder | Tom Tien-Cheng Chiu, Jeffrey Nguyen | 2000-11-07 |
| 6121796 | Power-saving dynamic circuit | Michael Kevin Ciraula | 2000-09-19 |
| 6111444 | Edge triggered latch | Eric Bernard Schorn | 2000-08-29 |
| 6094062 | Coupled noise reduction circuitry | Eric Bernard Schorn | 2000-07-25 |
| 6087855 | High performance dynamic multiplexers without clocked NFET | Marlin Wayne Frederick, Jr., Eric Bernard Schorn | 2000-07-11 |
| 5901079 | Skewed memory cell apparatus and method | Tom Tien-Cheng Chiu, Jeffrey Nguyen | 1999-05-04 |
| 5896046 | Latch structure for ripple domino logic | Andrew A. Bjorksten, Michael Kevin Ciraula, Christopher McCall Durham | 1999-04-20 |
| 5892372 | Creating inversions in ripple domino logic | Michael Kevin Ciraula, George McNeil Lattimore, Robert P. Masleid | 1999-04-06 |
| 5818264 | Dynamic circuit having improved noise immunity and method therefor | Michael Kevin Ciraula | 1998-10-06 |
| 5764549 | Fast floating point result alignment apparatus | Andrew A. Bjorksten, Martin S. Schmookler | 1998-06-09 |
| 5757205 | Power-saving dynamic circuit | Michael Kevin Ciraula | 1998-05-26 |