Issued Patents All Time
Showing 1–25 of 249 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10756095 | SRAM cell with T-shaped contact | Thomas J. Aton, Scott Jessen | 2020-08-25 |
| 10748913 | SRAM cell with T-shaped contact | Thomas J. Aton, Scott Jessen | 2020-08-18 |
| 10629250 | SRAM cell having an n-well bias | Anand Seshadri | 2020-04-21 |
| 10199380 | SRAM cell with T-shaped contact | Thomas J. Aton, Scott Jessen | 2019-02-05 |
| 10163911 | SRAM cell with T-shaped contact | Thomas J. Aton, Scott Jessen | 2018-12-25 |
| 9858986 | Integrated circuit with low power SRAM | Srinivasa Raghavan Sridhara | 2018-01-02 |
| 9236113 | Read assist for an SRAM using a word line suppression circuit | Lakshmikantha V. Holla, Vinod Menezes, Michael Patrick Clinton | 2016-01-12 |
| 9124263 | Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same | Andrew Marshall | 2015-09-01 |
| 9082507 | Read assist circuit for an SRAM, including a word line suppression circuit | Lakshmikantha V. Holla, Vinod Menezes, Michael Patrick Clinton | 2015-07-14 |
| 9059032 | SRAM cell parameter optimization | Puneet Kohli, Amitava Chatterjee | 2015-06-16 |
| 8945999 | SRAM cell with different crystal orientation than associated logic | — | 2015-02-03 |
| 8891288 | 8T SRAM cell with one word line | — | 2014-11-18 |
| 8891287 | SRAM cell having a p-well bias | Anand Seshadri | 2014-11-18 |
| 8873279 | 8T SRAM cell with one word line | — | 2014-10-28 |
| 8755239 | Read assist circuit for an SRAM | Lakshmikantha V. Holla, Vinod Menezes, Michael Patrick Clinton | 2014-06-17 |
| 8724375 | SRAM cell having an N-well bias | Anand Seshadri | 2014-05-13 |
| 8654572 | 10T SRAM cell with near dual port functionality | — | 2014-02-18 |
| 8654569 | 10T SRAM cell with near dual port functionality | — | 2014-02-18 |
| 8654568 | 10T SRAM cell with near dual port functionality | — | 2014-02-18 |
| 8535990 | SRAM cell with different crystal orientation than associated logic | — | 2013-09-17 |
| 8492205 | Offset geometries for area reduction in memory arrays | Robert R. Garcia | 2013-07-23 |
| 8437213 | Characterization of bits in a functional memory | Xiaowei Deng, Wah Kit Loh | 2013-05-07 |
| 8437214 | Memory cell employing reduced voltage | Donald George Mikan, Jr., Hugh Mair, Michael Patrick Clinton | 2013-05-07 |
| 8380478 | Statistical evaluation of circuit robustness separating local and global variation | — | 2013-02-19 |
| 8379467 | Structure and methods for measuring margins in an SRAM bit | Xiaowei Deng, Wah Kit Loh | 2013-02-19 |