Issued Patents All Time
Showing 25 most recent of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12057443 | ESD protection circuit with isolated SCR for negative voltage operation | Akram A. Salman, Farzan Farbiz, Xiaoju Wu | 2024-08-06 |
| 11302688 | ESD protection circuit with isolated SCR for negative voltage operation | Akram A. Salman, Farzan Farbiz, Xiaoju Wu | 2022-04-12 |
| 11049852 | ESD protection circuit with isolated SCR for negative voltage operation | Akram A. Salman, Farzan Farbiz, Xiaoju Wu | 2021-06-29 |
| 10608110 | I-shaped gate electrode for improved sub-threshold MOSFET performance | — | 2020-03-31 |
| 10128145 | Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells | Kamel Benaissa | 2018-11-13 |
| 10083951 | ESD protection circuit with isolated SCR for negative voltage operation | Akram A. Salman, Farzan Farbiz, Xiaoju Wu | 2018-09-25 |
| 9865507 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Pinghai Hao, Sameer Pendharkar | 2018-01-09 |
| 9768296 | I-shaped gate electrode for improved sub-threshold MOSFET performance | — | 2017-09-19 |
| 9721849 | High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit | Derek W. Robinson | 2017-08-01 |
| 9583596 | Drain extended CMOS with counter-doped drain extension | Philipp Steinmann, Sameer Pendharkar | 2017-02-28 |
| 9577094 | Low cost demos transistor with improved CHC immunity | Shaoping Tang, Imran Khan, Kaiping Liu | 2017-02-21 |
| 9461035 | High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit | Derek W. Robinson | 2016-10-04 |
| 9431302 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Pinghai Hao, Sameer Pendharkar | 2016-08-30 |
| 9412668 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Pinghai Hao, Sameer Pendharkar | 2016-08-09 |
| 9397164 | Deep collector vertical bipolar transistor with enhanced gain | Brian Edward Hornung, Xiang-Zheng Bo, Alwin Tsao | 2016-07-19 |
| 9245755 | Deep collector vertical bipolar transistor with enhanced gain | Brian Edward Hornung, Xiang-Zheng Bo, Alwin Tsao | 2016-01-26 |
| 9231054 | Drain extended CMOS with counter-doped drain extension | Philipp Steinmann, Sameer Pendharkar | 2016-01-05 |
| 9202912 | Low cost demos transistor with improved CHC immunity | Shaoping Tang, Imran Khan, Kaiping Liu | 2015-12-01 |
| 9099523 | ESD protection circuit with isolated SCR for negative voltage operation | Akram A. Salman, Farzan Farbiz, Xiaoju Wu | 2015-08-04 |
| 9064726 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Pinghai Hao, Sameer Pendharkar | 2015-06-23 |
| 9059032 | SRAM cell parameter optimization | Theodore W. Houston, Puneet Kohli | 2015-06-16 |
| 8975135 | Analog floating-gate capacitor with improved data retention in a silicided integrated circuit | Kaiping Liu, Imran Khan | 2015-03-10 |
| 8933510 | DEMOS formed with a through gate implant | Pinghai Hao, Imran Khan | 2015-01-13 |
| 8860147 | Semiconductor interconnect | Howard L. Tigelaar, Victor Sutcliffe | 2014-10-14 |
| 8779550 | Analog floating-gate capacitor with improved data retention in a silicided integrated circuit | Kaiping Liu, Imran Khan | 2014-07-15 |