Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

US Patent 9064726 · Granted Jun 23, 2015

Estimated economic value: $18,712,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electrostatic discharge guard ring with snapback protection2025
Gallium nitride transistor with a doped region2024
Gallium nitride transistor with a doped region2024
Electrostatic discharge guard ring with complementary drain extended devices2024
ESD protection circuit with isolated SCR for negative voltage operation2024
Gallium nitride (GaN) based transistor with multiple p-GaN blocks2024
Trench gate trench field plate vertical MOSFET2024
Superlattice photo detector2024
Gallium nitride transistor with a doped region2023
Gallium nitride transistor with a doped region2023
Electrostatic discharge guard ring with snapback protection2023
Laterally diffused metal oxide semiconductor with gate poly contact within sourc2023