Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12166119 | Gallium nitride transistor with a doped region | Dong Seup Lee, Jungwoo Joh, Sameer Pendharkar | 2024-12-10 |
| 11769824 | Gallium nitride transistor with a doped region | Dong Seup Lee, Jungwoo Joh, Sameer Pendharkar | 2023-09-26 |
| 11067620 | HEMT wafer probe current collapse screening | Dong Seup Lee, Jungwoo Joh, Sameer Pendharkar | 2021-07-20 |
| 10964803 | Gallium nitride transistor with a doped region | Dong Seup Lee, Jungwoo Joh, Sameer Pendharkar | 2021-03-30 |
| 10861943 | Transistor with multiple GaN-based alloy layers | Dong Seup Lee, Jungwoo Joh, Sameer Pendharkar | 2020-12-08 |
| 10714474 | High voltage CMOS with triple gate oxide | Binghua Hu, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Benjamin Jacobs | 2020-07-14 |
| 10312095 | Recessed solid state apparatuses | Dong Seup Lee, Yoshikazu Kondo, Sameer Pendharkar | 2019-06-04 |
| 10134596 | Recessed solid state apparatuses | Dong Seup Lee, Yoshikazu Kondo, Sameer Pendharkar | 2018-11-20 |
| 9865507 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Sameer Pendharkar, Amitava Chatterjee | 2018-01-09 |
| 9842895 | Single photomask high precision thin film resistor | Fuchao Wang, Duofeng Yue | 2017-12-12 |
| 9741718 | High voltage CMOS with triple gate oxide | Binghua Hu, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Benjamin Jacobs | 2017-08-22 |
| 9431302 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Sameer Pendharkar, Amitava Chatterjee | 2016-08-30 |
| 9412668 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Sameer Pendharkar, Amitava Chatterjee | 2016-08-09 |
| 9305688 | Single photomask high precision thin film resistor | Fuchao Wang, Duofeng Yue | 2016-04-05 |
| 9184163 | Low cost transistors | Sameer Pendharkar | 2015-11-10 |
| 9117687 | High voltage CMOS with triple gate oxide | Binghua Hu, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Benjamin Jacobs | 2015-08-25 |
| 9117691 | Low cost transistors | Sameer Pendharkar | 2015-08-25 |
| 9076760 | JFET having width defined by trench isolation | Binghua Hu, Sameer Pendharkar | 2015-07-07 |
| 9064726 | Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure | Sameer Pendharkar, Amitava Chatterjee | 2015-06-23 |
| 8946805 | Reduced area single poly EEPROM | Jozef Mitros, Keith Jarreau | 2015-02-03 |
| 8933510 | DEMOS formed with a through gate implant | Amitava Chatterjee, Imran Khan | 2015-01-13 |
| 8878283 | Quasi-vertical gated NPN-PNP ESD protection device | Marie Denison | 2014-11-04 |
| 8530296 | High voltage transistor using diluted drain | Sameer Pendharkar, Binghua Hu, Qingfeng Wang | 2013-09-10 |
| 8399924 | High voltage transistor using diluted drain | Sameer Pendharkar, Binghua Hu, Qingfeng Wang | 2013-03-19 |
| 8134212 | Implanted well breakdown in high voltage devices | Seetharaman Sridhar, James Robert Todd | 2012-03-13 |