Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8110857 | Low noise JFET | Imran Khan, Joe R. Trogolo | 2012-02-07 |
| 7989853 | Integration of high voltage JFET in linear bipolar CMOS process | Sameer Pendharkar, Philip L. Hower, Marie Denison | 2011-08-02 |
| 7968936 | Quasi-vertical gated NPN-PNP ESD protection device | Marie Denison | 2011-06-28 |
| 7939863 | Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process | Marie Denison | 2011-05-10 |
| 7786507 | Symmetrical bi-directional semiconductor ESD protection device | Marie Denison | 2010-08-31 |
| 7745274 | Gate self aligned low noise JFET | Xiaoju Wu, Fan-Chi Hou | 2010-06-29 |
| 7670888 | Low noise JFET | Imran Khan, Joe R. Trogolo | 2010-03-02 |
| 7598547 | Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device | Sameer Pendharker, Xiaoju Wu | 2009-10-06 |
| 7307309 | EEPROM with etched tunneling window | Jozef Mitros, Xiaoju Wu | 2007-12-11 |
| 7268394 | JFET structure for integrated circuit and fabrication method | Fan-Chi Hou, Imran Khan | 2007-09-11 |
| 7244651 | Fabrication of an OTP-EPROM having reduced leakage current | Xiaoju Wu, Jozef Mitros | 2007-07-17 |
| 7235451 | Drain extended MOS devices with self-aligned floating region and fabrication methods therefor | Shanjen Pan, Sameer Pendharkar | 2007-06-26 |
| 7208364 | Methods of fabricating high voltage devices | Shanjen Pan, Sameer Pendharkar, James Robert Todd | 2007-04-24 |
| 7164160 | Integrated circuit device with a vertical JFET | Sameer Pendharker, Xiaoju Wu | 2007-01-16 |
| 7135373 | Reduction of channel hot carrier effects in transistor devices | Shanjen Pan, Sameer Pendharkar | 2006-11-14 |
| 7122862 | Reduction of channel hot carrier effects in transistor devices | Shanjen Pan, Sameer Pendharkar | 2006-10-17 |
| 7045418 | Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor | Jozef Mitros, Weidong Tian, Victor Ivanov | 2006-05-16 |
| 7018880 | Method for manufacturing a MOS transistor having reduced 1/f noise | Larry B. Anderson, Fan-Chi Hou, Xiaoju Wu, Yvonne Patton, Shanjen Pan +1 more | 2006-03-28 |
| 7005354 | Depletion drain-extended MOS transistors and methods for making the same | Shanjen Pan, James Robert Todd, Sameer Pendharkar, Tsutomu Kubota | 2006-02-28 |
| 6885054 | Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same | Xiaoju Wu, Imran Khan | 2005-04-26 |
| 6861303 | JFET structure for integrated circuit and fabrication method | Fan-Chi Hou, Imran Khan | 2005-03-01 |
| 6794700 | Capacitor having a dielectric layer including a group 17 element | Eric Beach, Weidong Tian | 2004-09-21 |