Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8110857 | Low noise JFET | Pinghai Hao, Imran Khan | 2012-02-07 |
| 7704813 | Reliable high-voltage junction field effect transistor and method of manufacturing therefor | Kaiyuan Chen, Tathagata Chatterjee, Steve Merchant | 2010-04-27 |
| 7670888 | Low noise JFET | Pinghai Hao, Imran Khan | 2010-03-02 |
| 7670890 | Silicide block isolated junction field effect transistor source, drain and gate | Badih El-Kareh, Hiroshi Yasuda, Scott Balster, Philipp Steinmann | 2010-03-02 |
| 7615805 | Versatile system for optimizing current gain in bipolar transistor structures | Tathagata Chatterjee, Lily Springer, Jeffrey P. Smith | 2009-11-10 |
| 7615425 | Open source/drain junction field effect transistor | Hiroshi Yasuda, Badih El-Kareh, Philipp Steinmann | 2009-11-10 |
| 7595649 | Method to accurately estimate the source and drain resistance of a MOSFET | Tathagata Chatterjee, Kaiyuan Chen, Henry Litzmann Edwards | 2009-09-29 |
| 7312481 | Reliable high-voltage junction field effect transistor and method of manufacture therefor | Kaiyuan Chen, Tathagata Chatterjee, Steve Merchant | 2007-12-25 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures | Tathagata Chatterlee, Lily Springer, Jeff Smith | 2007-06-05 |
| 7195984 | Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies | William Loftin, William F. Kyser, Jr. | 2007-03-27 |
| 6869851 | Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps | Lily Springer, Jeff Smith, Sheldon Douglas Haynie | 2005-03-22 |
| 6867100 | System for high-precision double-diffused MOS transistors | Henry Litzmann Edwards, Sameer Pendharkar, Tathagata Chatterjee, Taylor R. Efland | 2005-03-15 |
| 6856000 | Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies | William Loftin, William F. Kyser, Jr. | 2005-02-15 |
| 6716709 | Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps | Lily Springer, Jeff Smith, Sheldon Douglas Haynie | 2004-04-06 |
| 5539237 | Schottky diode with guard ring | James Robert Todd, Andrew Marshall, Eric Soenen | 1996-07-23 |
| 5455447 | Vertical PNP transistor in merged bipolar/CMOS technology | Louis N. Hutter | 1995-10-03 |
| 5418185 | Method of making schottky diode with guard ring | James Robert Todd, Andrew Marshall, Eric Soenen | 1995-05-23 |
| 5256582 | Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate | Dan M. Mosher, Cornelia H. Blanton, Larry Latham, David R. Cotton, Bob Todd | 1993-10-26 |
| 5181095 | Complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate | Dan M. Mosher, Larry Latham, Bob Todd, Cornelia H. Blanton, David R. Cotton | 1993-01-19 |
| 5153697 | Integrated circuit that combines multi-epitaxial power transistors with logic/analog devices, and a process to produce same | Dan M. Mosher, Cornelia H. Blanton, Larry Latham, David R. Cotton | 1992-10-06 |
| 5034337 | Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices | Dan M. Mosher, Cornelia H. Blanton, Larry Latham, David R. Cotton | 1991-07-23 |
| 4939099 | Process for fabricating isolated vertical bipolar and JFET transistors | Michael R. Seacrist, Kenneth Bell | 1990-07-03 |
| 4855244 | Method of making vertical PNP transistor in merged bipolar/CMOS technology | Louis N. Hutter | 1989-08-08 |
| 4660065 | Hall effect device with surface potential shielding layer | Fernando D. Carvajal | 1987-04-21 |
| 4407005 | N-Channel JFET device having a buried channel region, and method for making same | Kenneth Bell | 1983-09-27 |