Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7279738 | Semiconductor device with an analog capacitor | Imran Khan, James Todd, Jozef Mitros, William Nehrer | 2007-10-09 |
| 6979615 | System and method for forming a semiconductor with an analog capacitor using fewer structure steps | Imran Khan, James Todd, Jozef Mitros, William Nehrer | 2005-12-27 |
| 6737326 | Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect | Philipp Steinmann, Stuart M. Jacobsen, Fred D. Bailey | 2004-05-18 |
| 6706635 | Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis | Imran Khan, William Nehrer, James Todd, Weidong Tian | 2004-03-16 |
| 6683380 | Integrated circuit with bonding layer over active circuitry | Taylor R. Efland, Donald C. Abbott, Walter Bucksch, Marco Corsi, Chi-Cheong Shen +5 more | 2004-01-27 |
| 6534364 | Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region | John P. Erdeljac | 2003-03-18 |
| 6432791 | Integrated circuit capacitor and method | Peter Ying, Imran Khan | 2002-08-13 |
| 6424005 | LDMOS power device with oversized dwell | Chin-Yu Tsai, Taylor R. Efland, Sameer Pendharkar, John P. Erdeljac, Jozef Mitros +1 more | 2002-07-23 |
| 6396109 | Isolated NMOS transistor fabricated in a digital BiCMOS process | Jeffrey P. Smith | 2002-05-28 |
| 6352887 | Merged bipolar and CMOS circuit and method | Peter Ying, Marco Corsi, Imran Khan | 2002-03-05 |
| 6284617 | Metalization outside protective overcoat for improved capacitors and inductors | John P. Erdeljac, M. Ali Khatibzadeh, John Kenneth Arch | 2001-09-04 |
| 6284669 | Power transistor with silicided gate and contacts | John P. Erdeljac, Jeffrey P. Smith, Han-Tzong Yuan, Jau-Yuann Yang, Taylor R. Efland +3 more | 2001-09-04 |
| 6236101 | Metallization outside protective overcoat for improved capacitors and inductors | John P. Erdeljac, M. Ali Khatibzadeh, John Kenneth Arch | 2001-05-22 |
| 6153451 | Transistor with increased operating voltage and method of fabrication | John P. Erdeljac, Jeffrey P. Smith | 2000-11-28 |
| 6144100 | Integrated circuit with bonding layer over active circuitry | Chi-Cheong Shen, Donald C. Abbott, Walter Bucksch, Marco Corsi, Taylor R. Efland +4 more | 2000-11-07 |
| 6033946 | Method for fabricating an isolated NMOS transistor on a digital BiCMOS process | Jeffrey P. Smith | 2000-03-07 |
| 6025231 | Self aligned DMOS transistor and method of fabrication | John P. Erdeljac, James Robert Todd | 2000-02-15 |
| 5929506 | Isolated vertical PNP transistor and methods for making same in a digital BiCMOS process | Jeffrey P. Smith | 1999-07-27 |
| 5880002 | Method for making isolated vertical PNP transistor in a digital BiCMOS process | Jeffrey P. Smith | 1999-03-09 |
| 5825065 | Low voltage DMOS transistor | Marco Corsi, John P. Erdeljac | 1998-10-20 |
| 5719421 | DMOS transistor with low on-resistance and method of fabrication | John P. Erdeljac | 1998-02-17 |
| 5702959 | Method for making an isolated vertical transistor | Jeffrey P. Smith | 1997-12-30 |
| 5614755 | High voltage Shottky diode | Marco Corsi | 1997-03-25 |
| 5576233 | Method for making an EEPROM with thermal oxide isolated floating gate | John P. Erdeljac | 1996-11-19 |
| 5574298 | Substrate contact for gate array base cell and method of forming same | Masashi Hashimoto, S. Shivaling Mahant-Shetti | 1996-11-12 |