Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5554873 | Semiconductor device having polysilicon resistor with low temperature coefficient | John P. Erdeljac | 1996-09-10 |
| 5527722 | Method of fabrication of a semiconductor device having high-and low-voltage MOS transistors | Jeffrey P. Smith | 1996-06-18 |
| 5528064 | Structure for protecting integrated circuits from electro-static discharge | Frank L. Thiel, Michael R. Kay | 1996-06-18 |
| 5489547 | Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient | John P. Erdeljac | 1996-02-06 |
| 5472887 | Method of fabricating semiconductor device having high-and low-voltage MOS transistors | Jeffrey P. Smith | 1995-12-05 |
| 5455447 | Vertical PNP transistor in merged bipolar/CMOS technology | Joe R. Trogolo | 1995-10-03 |
| 5436179 | Semiconductor process for manufacturing semiconductor devices with increased operating voltages | John P. Erdeljac | 1995-07-25 |
| 5408125 | Semiconductor process for manufacturing semiconductor device with increased operating voltages | John P. Erdeljac | 1995-04-18 |
| 5330922 | Semiconductor process for manufacturing semiconductor devices with increased operating voltages | John P. Erdeljac | 1994-07-19 |
| 5317180 | Vertical DMOS transistor built in an n-well MOS-based BiCMOS process | John P. Erdeljac | 1994-05-31 |
| 5296393 | Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods | Michael C. Smayling, Georges Falessi, James Robert Todd, Manuel J. Torreno, Jr. deceased | 1994-03-22 |
| 5272098 | Vertical and lateral insulated-gate, field-effect transistors, systems and methods | Michael C. Smayling, James Robert Todd | 1993-12-21 |
| 5171699 | Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication | John P. Erdeljac | 1992-12-15 |
| 5057443 | Method for fabricating a trench bipolar transistor | — | 1991-10-15 |
| 4994887 | High voltage merged bipolar/CMOS technology | Mark Edward Gibson, Jeffrey P. Smith, Shiu-Hang Yan, Arnold C. Conway, John P. Erdeljac +4 more | 1991-02-19 |
| 4980747 | Deep trench isolation with surface contact to substrate | James D. Goon, Shiu-Hang Yan, Gopal K. Rao | 1990-12-25 |
| 4929996 | Trench bipolar transistor | — | 1990-05-29 |
| 4926233 | Merged trench bipolar-CMOS transistor fabrication process | — | 1990-05-15 |
| 4855244 | Method of making vertical PNP transistor in merged bipolar/CMOS technology | Joe R. Trogolo | 1989-08-08 |
| 4819052 | Merged bipolar/CMOS technology using electrically active trench | — | 1989-04-04 |
| 4805071 | High voltage capacitor for integrated circuits | John P. Erdeljac | 1989-02-14 |