Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6604233 | Method for optimizing the integrated circuit chip size for efficient manufacturing | Carl A. Vickery, Robert A. Tuerck, Troy M. Loveday, Jesse Rojas | 2003-08-05 |
| 4994887 | High voltage merged bipolar/CMOS technology | Louis N. Hutter, Mark Edward Gibson, Jeffrey P. Smith, Shiu-Hang Yan, Arnold C. Conway +4 more | 1991-02-19 |
| 4980747 | Deep trench isolation with surface contact to substrate | Louis N. Hutter, Shiu-Hang Yan, Gopal K. Rao | 1990-12-25 |