Issued Patents All Time
Showing 25 most recent of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9076671 | Power integrated circuit including series-connected source substrate and drain substrate power mosfets | Christopher Boguslaw Kocon, Marie Denison | 2015-07-07 |
| 8928075 | Power integrated circuit including series-connected source substrate and drain substrate power MOSFETs | Christopher Boguslaw Kocon, Marie Denison | 2015-01-06 |
| 8304868 | Multi-component electronic system having leadframe with support-free with cantilever leads | Michael G. Amaro, Steven Kummerl, Sreenivasan K. Koduri | 2012-11-06 |
| 8253193 | MOS transistor with gate trench adjacent to drain extension field insulation | Marie Denison, Sameer Pendharkar, Binghua Hu, Sridhar Seetharaman | 2012-08-28 |
| 8173510 | Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric | Marie Denison | 2012-05-08 |
| 8124482 | MOS transistor with gate trench adjacent to drain extension field insulation | Marie Denison, Sameer Pendharkar, Binghua Hu, Sridhar Seetharaman | 2012-02-28 |
| 7893499 | MOS transistor with gate trench adjacent to drain extension field insulation | Marie Denison, Sameer Pendharkar, Binghua Hu, Sridhar Seetharaman | 2011-02-22 |
| 7888732 | Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric | Marie Denison | 2011-02-15 |
| 7514329 | Robust DEMOS transistors and method for making the same | Sameer Pendharkar, Ramanathan Ramani | 2009-04-07 |
| 7514292 | Individualized low parasitic power distribution lines deposited over active integrated circuits | Milton L. Buschbom, Sameer Pendharkar | 2009-04-07 |
| 7268045 | N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects | Philip L. Hower | 2007-09-11 |
| 7238986 | Robust DEMOS transistors and method for making the same | Sameer Pendharkar, Ramanathan Ramani | 2007-07-03 |
| 7195965 | Premature breakdown in submicron device geometries | John Lin, Philip L. Hower, Sameer Pendharkar, Vladimir Bolkhovsky | 2007-03-27 |
| 7135759 | Individualized low parasitic power distribution lines deposited over active integrated circuits | Milton L. Buschbom, Sameer Pendharkar | 2006-11-14 |
| 7060607 | Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface | — | 2006-06-13 |
| 7045903 | Integrated power circuits with distributed bonding and current flow | Sameer Pendharkar | 2006-05-16 |
| 6972484 | Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface | — | 2005-12-06 |
| 6958515 | N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects | Philip L. Hower | 2005-10-25 |
| 6930005 | Low cost fabrication method for high voltage, high drain current MOS transistor | Jozef Mitros, Imran Khan | 2005-08-16 |
| 6908859 | Low leakage power transistor and method of forming | Sameer Pendharkar, William Nehrer | 2005-06-21 |
| 6873021 | MOS transistors having higher drain current without reduced breakdown voltage | Jozef Mitros, Imran Khan | 2005-03-29 |
| 6867100 | System for high-precision double-diffused MOS transistors | Henry Litzmann Edwards, Sameer Pendharkar, Joe R. Trogolo, Tathagata Chatterjee | 2005-03-15 |
| 6784493 | Line self protecting multiple output power IC architecture | David Alexander Grant, Ramanathan Ramani, Dale J. Skelton, David D. Briggs, Chin-Yu Tsai | 2004-08-31 |
| 6784539 | Thermally enhanced semiconductor chip having integrated bonds over active circuits | — | 2004-08-31 |
| 6770935 | Array of transistors with low voltage collector protection | David Alexander Grant, Ramanathan Ramani, Chin-Yu Tsai, Dale J. Skelton | 2004-08-03 |