Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10534787 | Remote data delivery system | David J. Kasik | 2020-01-14 |
| 10127331 | 3D models utilizing 3D markers to indicate engineering requirements | Lloyd James Milton, Andrew A. Austill, Anthony Robert Davies, Gregory Dean Lane | 2018-11-13 |
| 9954448 | Current mode regulator | Ross E. Teggatz, Amer Atrash, Wayne T. Chen | 2018-04-24 |
| 9343988 | Current mode regulator | Ross E. Teggatz, Amer Atrash, Wayne T. Chen | 2016-05-17 |
| 6784493 | Line self protecting multiple output power IC architecture | Taylor R. Efland, David Alexander Grant, Ramanathan Ramani, Dale J. Skelton, Chin-Yu Tsai | 2004-08-31 |
| 6750553 | Semiconductor device which minimizes package-shift effects in integrated circuits by using a thick metallic overcoat | Buddhika Abesingha, Gabriel A. Rincon-Mora, Roy Alan Hastings | 2004-06-15 |
| 6734705 | Technique for improving propagation delay of low voltage to high voltage level shifters | Mark Pulkin | 2004-05-11 |
| 6710427 | Distributed power device with dual function minority carrier reduction | Taylor R. Efland, David Alexander Grant, Ramanathan Ramani, Chin-Yu Tsai, Dale J. Skelton | 2004-03-23 |
| 6709900 | Method of fabricating integrated system on a chip protection circuit | Taylor R. Efland, David Alexander Grant, Ramanathan Ramani, Dale J. Skelton, Chin-Yu Tsai | 2004-03-23 |
| 6661216 | Apparatus and method for controlling startup of a precharged switching regulator | David Alexander Grant, Ayesha I. Mayhugh | 2003-12-09 |
| 6432753 | Method of minimizing package-shift effects in integrated circuits by using a thick metallic overcoat | Buddhika Abesingha, Gabriel A. Rincon-Mora, Roy Alan Hastings | 2002-08-13 |
| 6140683 | Efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection | Charvaka Duvvury, Fernando D. Carvajal | 2000-10-31 |
| 6087852 | Multiplexing a single output node with multiple output circuits with varying output voltages | Fernando D. Carvajal, Chao-Chih Chiu | 2000-07-11 |
| 6071768 | Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection | Charvaka Duvvury, Fernando D. Carvajal | 2000-06-06 |
| 6064249 | Lateral DMOS design for ESD protection | Charvaka Duvvury, Fred Carvajal | 2000-05-16 |
| 5537067 | Signal driver circuit operable to control signal rise and fall times | Fernando D. Carvajal | 1996-07-16 |