Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10937905 | Transistor having double isolation with one floating isolation | Yongxi Zhang, Philip L. Hower, Sameer Pendharkar, John Lin, Guru Mathur +1 more | 2021-03-02 |
| 10319809 | Structures to avoid floating resurf layer in high voltage lateral devices | Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Constantin Bulucea +2 more | 2019-06-11 |
| 9985028 | Diluted drift layer with variable stripe widths for power transistors | Yongxi Zhang, Sameer Pendharkar | 2018-05-29 |
| 9876071 | Structures to avoid floating RESURF layer in high voltage lateral devices | Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Constantin Bulucea +2 more | 2018-01-23 |
| 9653577 | Diluted drift layer with variable stripe widths for power transistors | Yongxi Zhang, Sameer Pendharkar | 2017-05-16 |
| 9431480 | Diluted drift layer with variable stripe widths for power transistors | Yongxi Zhang, Sameer Pendharkar | 2016-08-30 |
| 8847359 | High voltage bipolar transistor and method of fabrication | Hiroshi Yasuda, Philipp Steinmann, Badih El-Kareh | 2014-09-30 |
| 8703568 | Advanced CMOS using super steep retrograde wells | Jeffrey A. Babcock, Angelo Pinto, Alfred Haeusler, Gregory E. Howard | 2014-04-22 |
| 8450179 | Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication | Badih El-Kareh, Hiroshi Yasuda | 2013-05-28 |
| 8294218 | Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection | Badih El-Kareh, Hiroshi Yasuda, Manfred Schiekofer | 2012-10-23 |
| 8247300 | Control of dopant diffusion from buried layers in bipolar integrated circuits | Jeffrey A. Babcock, Angelo Pinto, Manfred Schiekofer, Gregory E. Howard, Alfred Hausler | 2012-08-21 |
| 8129246 | Advanced CMOS using super steep retrograde wells | Jeffrey A. Babcock, Angelo Pinto, Alfred Haeusler, Gregory E. Howard | 2012-03-06 |
| 8012842 | Method for fabricating isolated integrated semiconductor structures | Badih El-Kareh, Hiroshi Yasuda | 2011-09-06 |
| 7883977 | Advanced CMOS using super steep retrograde wells | Jeffrey A. Babcock, Angelo Pinto, Alfred Haeusler, Gregory E. Howard | 2011-02-08 |
| 7772057 | Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection | Badih El-Kareh, Hiroshi Yasuda, Manfred Schiekofer | 2010-08-10 |
| 7736986 | Integrated stacked capacitor and method of fabricating same | Christoph Dirnecker, Jeffrey A. Babcock | 2010-06-15 |
| 7670890 | Silicide block isolated junction field effect transistor source, drain and gate | Badih El-Kareh, Hiroshi Yasuda, Philipp Steinmann, Joe R. Trogolo | 2010-03-02 |
| 7655523 | Advanced CMOS using super steep retrograde wells | Jeffrey A. Babcock, Angelo Pinto, Alfred Haeusler, Gregory E. Howard | 2010-02-02 |
| 7501324 | Advanced CMOS using super steep retrograde wells | Jeffrey A. Babcock, Angelo Pinto, Alfred Haeusler, Gregory E. Howard | 2009-03-10 |
| 7498639 | Integrated BiCMOS semiconductor circuit | Philipp Steinmann, Badih El-Kareh, Thomas Scharnagl, Michael Schmitt | 2009-03-03 |
| 7422972 | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits | Jeffrey A. Babcock, Angelo Pinto, Gregory E. Howard, Philipp Steinmann | 2008-09-09 |
| 7312119 | Stacked capacitor and method of fabricating same | Badih El-Kareh, Philipp Steinman, Christoph Dirnecker | 2007-12-25 |
| 7227241 | Integrated stacked capacitor and method of fabricating same | Christoph Dirnecker, Jeffrey A. Babcock | 2007-06-05 |
| 7217322 | Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer | Jeffrey A. Babcock, Alfred Haeusler, Angelo Pinto, Manfred Schiekofer, Philipp Steinmann +1 more | 2007-05-15 |
| 7199430 | Advanced CMOS using super steep retrograde wells | Jeffrey A. Babcock, Angelo Pinto, Alfred Haeusler, Gregory E. Howard | 2007-04-03 |