Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9865584 | Contact array optimization for ESD devices | He Lin, Kun-Ming Chen, Chao-Wei Wu, Dening Wang, Andy Strachan +1 more | 2018-01-09 |
| 8664080 | Vertical ESD protection device | Toshiyuki Tani, Hiroshi Yamasaki, Kentaro Takahashi | 2014-03-04 |
| 8273623 | Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor | David Leonard Larkin, Makoto Takemura, Ashish V. Gokhale, Dhaval A. Saraiya | 2012-09-25 |
| 8114731 | Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor | David Leonard Larkin, Makoto Takemura, Ashish V. Gokhale, Dhaval A. Saraiya | 2012-02-14 |
| 7895554 | Verification method with the implementation of well voltage pseudo diodes | Wen-Hwa Chu, Shaibal Barua, James Garrett Homack | 2011-02-22 |
| 7615805 | Versatile system for optimizing current gain in bipolar transistor structures | Joe R. Trogolo, Tathagata Chatterjee, Jeffrey P. Smith | 2009-11-10 |
| 7562315 | Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout | Haim Horovitz, Robert G. Shaw, Sameer Pendharkar, Wen-Hwa Chu, Paul C. Mannas | 2009-07-14 |
| 7470991 | Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor | David Leonard Larkin, Makoto Takemura, Ashish V. Gokhale, Dhaval A. Saraiya | 2008-12-30 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures | Joe R. Trogolo, Tathagata Chatterlee, Jeff Smith | 2007-06-05 |
| 7164174 | Single poly-emitter PNP using dwell diffusion in a BiCMOS technology | — | 2007-01-16 |
| 6958269 | Memory device with reduced cell size | Josef Czeslaw Mitros, Imran Khan | 2005-10-25 |
| 6949424 | Single poly-emitter PNP using DWELL diffusion in a BiCMOS technology | — | 2005-09-27 |
| 6869851 | Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps | Joe R. Trogolo, Jeff Smith, Sheldon Douglas Haynie | 2005-03-22 |
| 6806541 | Field effect transistor with improved isolation structures | Binghua Hu, Chin-Yu Tsai, Jozef Mitros | 2004-10-19 |
| 6747308 | Single poly EEPROM with reduced area | Jozef Mitros, Roland Bucksch | 2004-06-08 |
| 6730569 | Field effect transistor with improved isolation structures | Binghua Hu, Chin-Yu Tsai, Jozef Mitros | 2004-05-04 |
| 6716709 | Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps | Jeff Smith, Sheldon Douglas Haynie, Joe R. Trogolo | 2004-04-06 |