Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10917052 | Dual device semiconductor structures with shared drain | Marc Tarabbia, Christian Larsen | 2021-02-09 |
| 10298184 | Dual device semiconductor structures with shared drain | Marc Tarabbia, Christian Larsen | 2019-05-21 |
| 9919913 | Fully depleted region for reduced parasitic capacitance between a poly-silicon layer and a substrate region | Marc Tarabbia | 2018-03-20 |
| 9853103 | Pinched doped well for a junction field effect transistor (JFET) isolated from the substrate | Marc Tarabbia, John L. Melanson | 2017-12-26 |
| 9275992 | Formation of electrical components on a semiconductor substrate by polishing to isolate the components | Marc Tarabbia | 2016-03-01 |
| 8765550 | N-channel erasable programmable non-volatile memory | Alan T. Mitchell, Jack Qian | 2014-07-01 |
| 8679929 | On current in one-time-programmable memory cells | Allan T. Mitchell, Weidong Tian | 2014-03-25 |
| 8664706 | Current in one-time-programmable memory cells | Allan T. Mitchell, Weidong Tian | 2014-03-04 |
| 8546222 | Electrically erasable programmable non-volatile memory | Allan T. Mitchell, Weidong Tian | 2013-10-01 |
| 7618870 | Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof | Sameer Pendharkar, James Robert Todd | 2009-11-17 |
| 7498652 | Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof | Sameer Pendharkar, James Robert Todd | 2009-03-03 |
| 7262471 | Drain extended PMOS transistor with increased breakdown voltage | Sameer Pendharkar, James Robert Todd | 2007-08-28 |
| 7235451 | Drain extended MOS devices with self-aligned floating region and fabrication methods therefor | Pinghai Hao, Sameer Pendharkar | 2007-06-26 |
| 7208364 | Methods of fabricating high voltage devices | Sameer Pendharkar, Pinghai Hao, James Robert Todd | 2007-04-24 |
| 7135373 | Reduction of channel hot carrier effects in transistor devices | Pinghai Hao, Sameer Pendharkar | 2006-11-14 |
| 7122862 | Reduction of channel hot carrier effects in transistor devices | Pinghai Hao, Sameer Pendharkar | 2006-10-17 |
| 7112480 | Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices | James Robert Todd, Sameer Pendharkar | 2006-09-26 |
| 7018880 | Method for manufacturing a MOS transistor having reduced 1/f noise | Pinghai Hao, Larry B. Anderson, Fan-Chi Hou, Xiaoju Wu, Yvonne Patton +1 more | 2006-03-28 |
| 7005354 | Depletion drain-extended MOS transistors and methods for making the same | James Robert Todd, Sameer Pendharkar, Tsutomu Kubota, Pinghai Hao | 2006-02-28 |
| 6969901 | Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices | James Robert Todd, Sameer Pendharkar | 2005-11-29 |
| 6803282 | Methods for fabricating low CHC degradation mosfet transistors | Jozef Mitros, James Robert Todd, Tsutomu Kubota | 2004-10-12 |