AC

Amitava Chatterjee

TI Texas Instruments: 104 patents #36 of 12,488Top 1%
📍 Plano, TX: #26 of 4,842 inventorsTop 1%
🗺 Texas: #419 of 125,132 inventorsTop 1%
Overall (All Time): #13,458 of 4,157,543Top 1%
104
Patents All Time

Issued Patents All Time

Showing 51–75 of 104 patents

Patent #TitleCo-InventorsDate
7018888 Method for manufacturing improved sidewall structures for use in semiconductor devices Brian E. Goodlin, Shirin Siddiqui, Jong Shik Yoon 2006-03-28
6987039 Forming lateral bipolar junction transistor in CMOS flow 2006-01-17
6873008 Asymmetrical devices for short gate length performance with disposable sidewall Theodore W. Houston 2005-03-29
6869840 Compensated-well electrostatic discharge protection devices Keith E. Kunz 2005-03-22
6858486 Vertical bipolar transistor formed using CMOS processes 2005-02-22
6794730 High performance PNP bipolar device fully compatible with CMOS process Youngmin Kim, Shaoping Tang, Seetharaman Sridhar 2004-09-21
6791383 Reduced gate leakage current in thin gate dielectric CMOS integrated circuits 2004-09-14
6767810 Method to increase substrate potential in MOS transistors used in ESD protection circuits Craig T. Salling, Youngmin Kim 2004-07-27
6753559 Transistor having improved gate structure Wei William Lee, Greg Hames, Qizhi He, Maureen A. Hanratty, Iqbal Ali 2004-06-22
6730555 Transistors having selectively doped channel regions Youngmin Kim 2004-05-04
6713334 Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask Mahalingam Nandakumar, Youngmin Kim 2004-03-30
6682980 Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant P.R. Chidambaram, Srinivasan Chakravarthi 2004-01-27
6649983 Vertical bipolar transistor formed using CMOS processes 2003-11-18
6646311 Vertical bipolar transistor formed using CMOS processes 2003-11-11
6639284 Compensated-well electrostatic discharge protection structure Keith E. Kunz 2003-10-28
6598214 Design method and system for providing transistors with varying active region lengths Sreedhar Natarajan 2003-07-22
6548359 Asymmetrical devices for short gate length performance with disposable sidewall Theodore W. Houston 2003-04-15
6514810 Buried channel PMOS transistor in dual gate CMOS with reduced masking steps Youngmin Kim 2003-02-04
6482724 Integrated circuit asymmetric transistors 2002-11-19
6479339 Use of a thin nitride spacer in a split gate embedded analog process Mahalingam Nandakumar 2002-11-12
6436746 Transistor having an improved gate structure and method of construction Wei William Lee, Greg Hames, Qizhi He, Maureen A. Hanratty, Iqbal Ali 2002-08-20
6420236 Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices Jerry Hu, Hong-Seon Yang, Ih-Chin Chen 2002-07-16
6413824 METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS Alec J. Morton, Mark S. Rodder, Taylor R. Efland, Chin-Yu Tsai, James R. Hellums 2002-07-02
6352900 Controlled oxide growth over polysilicon gates for improved transistor characteristics Manoj Mehrotra, Jerry Hu, Mark S. Rodder 2002-03-05
6313010 Integrated circuit insulator and method Somnath Nag, Ih-Chin Chen 2001-11-06