Issued Patents All Time
Showing 26–50 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8753944 | Pocket counterdoping for gate-edge diode leakage reduction | Mahalingam Nandakumar, Brian Edward Hornung, Terry James Bordelon, Jr. | 2014-06-17 |
| 8716097 | MOS transistors having reduced leakage well-substrate junctions | Terry James Bordelon, Jr. | 2014-05-06 |
| 8716827 | Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells | Kamel Benaissa | 2014-05-06 |
| 8592900 | Drain extended CMOS with counter-doped drain extension | Philipp Steinmann, Sameer Pendharkar | 2013-11-26 |
| 8114744 | Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom | Seetharaman Sridhar, Xiaoju Wu, Vladimir F. Drobny | 2012-02-14 |
| 8067279 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Alwin Tsao, Seetharaman Sridhar | 2011-11-29 |
| 8053322 | Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom | Vladimir F. Drobny, Phillipp Steinmann, Rick L. Wise | 2011-11-08 |
| 7859289 | Method for measuring interface traps in thin gate oxide MOSFETS | Tathagata Chatterjee | 2010-12-28 |
| 7795085 | Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs | Jong Shik Yoon, Kayvan Sadra, Shaoping Tang | 2010-09-14 |
| 7662688 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Alwin Tsao, Seetharaman Sridhar | 2010-02-16 |
| 7638402 | Sidewall spacer pullback scheme | Mahalingam Nandakumar, Terrence J. Riley | 2009-12-29 |
| 7514331 | Method of manufacturing gate sidewalls that avoids recessing | Jong Shik Yoon, Haowen Bu | 2009-04-07 |
| 7314800 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Alwin Tsao, Seetharaman Sridhar | 2008-01-01 |
| 7285830 | Lateral bipolar junction transistor in CMOS flow | — | 2007-10-23 |
| 7279397 | Shallow trench isolation method | Manoj Mehrotra | 2007-10-09 |
| 7229869 | Method for manufacturing a semiconductor device using a sidewall spacer etchback | Jong Shik Yoon, Shirin Siddiqui, Brian E. Goodlin, Karen Hildegard Ralston Kirmse | 2007-06-12 |
| 7216310 | Design method and system for optimum performance in integrated circuits that use power management | David B. Scott, Theodore W. Houston, Song Zhao, Shaoping Tang, Zhiqiang Wu | 2007-05-08 |
| 7193277 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Alwin Tsao, Seetharaman Sridhar | 2007-03-20 |
| 7141468 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Alwin Tsao, Seetharaman Sridhar | 2006-11-28 |
| 7112497 | Multi-layer reducible sidewall process | Freidoon Mehrad, Vivian Liu | 2006-09-26 |
| 7098099 | Semiconductor device having optimized shallow junction geometries and method for fabrication thereof | Brian Edward Hornung, Jong Shik Yoon, Deborah J. Riley | 2006-08-29 |
| 7045436 | Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) | Alwin Tsao, Manuel Quevedo-Lopez, Jong Shik Yoon, Shaoping Tang | 2006-05-16 |
| 7045410 | Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) | Freidoon Mehrad | 2006-05-16 |
| 7039888 | Modeling process for integrated circuit film resistors | Philipp Steinmann, Doug Weiser, Roland Bucksch | 2006-05-02 |
| 7029967 | Silicide method for CMOS integrated circuits | Song Zhao, Sue Crank, Kaiping Liu, Jiong-Ping Lu, Donald Miles +2 more | 2006-04-18 |