Issued Patents All Time
Showing 25 most recent of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412019 | Method and system for latch-up prevention | Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su +4 more | 2025-09-09 |
| 11615227 | Method and system for latch-up prevention | Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su +4 more | 2023-03-28 |
| 10872190 | Method and system for latch-up prevention | Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su +4 more | 2020-12-22 |
| 9385213 | Integrated circuits and manufacturing methods thereof | Chung-Cheng Wu, Ali Keshavarzi, Ka-Hing Fung, Ta-Pen Guo, Jiann-Tyng Tzeng +6 more | 2016-07-05 |
| 8804450 | Memory circuits having a diode-connected transistor with back-biased control | Steven Swei | 2014-08-12 |
| 8504972 | Standard cells having flexible layout architecture/boundaries | Yung-Chin Hou, Lee-Chung Lu, Li-Chun Tien | 2013-08-06 |
| 8432071 | Method and apparatus for energy harvest from ambient sources | Ming-Chieh Huang, Chan-Hong Chern | 2013-04-30 |
| 8411525 | Memory circuits having a diode-connected transistor with back-biased control | Steven Swei | 2013-04-02 |
| 8362573 | Integrated circuits and manufacturing methods thereof | Chung-Cheng Wu, Ali Keshavarzi, Ka-Hing Fung, Ta-Pen Guo, Jiann-Tyng Tzeng +6 more | 2013-01-29 |
| 8122406 | Generating models for integrated circuits with sensitivity-based minimum change to existing models | Bing J. Sheu, Jiann-Tyng Tzeng | 2012-02-21 |
| 7639056 | Ultra low area overhead retention flip-flop for power-down applications | Sumanth Katte Gururajarao, Hugh Mair, Uming Ko | 2009-12-29 |
| 7519925 | Integrated circuit with dynamically controlled voltage supply | Sami Issa, Uming Ko | 2009-04-14 |
| 7466578 | Methods and systems for read-only memory | Radu Avramescu | 2008-12-16 |
| 7407850 | N+ poly on high-k dielectric for semiconductor devices | Ramesh Venugopal, Christoph Wasshuber | 2008-08-05 |
| 7376038 | Fast access memory architecture | Sudha Thiruvengadam, Ramaprasath Vilangudipitchai, Uming Ko, Alice Wang | 2008-05-20 |
| 7307471 | Adaptive voltage control and body bias for performance and energy optimization | Gordon Gammie, Alice Wang, Uming Ko | 2007-12-11 |
| 7282905 | System and method for IDDQ measurement in system on a chip (SOC) design | Wei Chen, Hugh Mair, Uming Ko | 2007-10-16 |
| 7236396 | Area efficient implementation of small blocks in an SRAM array | Theodore W. Houston, Sudha Thiruvengadam | 2007-06-26 |
| 7216310 | Design method and system for optimum performance in integrated circuits that use power management | Amitava Chatterjee, Theodore W. Houston, Song Zhao, Shaoping Tang, Zhiqiang Wu | 2007-05-08 |
| 7180208 | Switch structure for reduced voltage fluctuation in power domains and sub-domains | Wei Chen, Hugh Mair, Uming Ko | 2007-02-20 |
| 7164291 | Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors | Hugh Mair, Rolf Lagerquist | 2007-01-16 |
| 7162652 | Integrated circuit dynamic parameter management in response to dynamic energy evaluation | Sami Issa, Uming Ko, Baher Haroun | 2007-01-09 |
| 7091766 | Retention register for system-transparent state retention | Uming Ko, Sumanth Katte Gururajarao, Hugh Mair | 2006-08-15 |
| 6989702 | Retention register with normal functionality independent of retention power supply | Uming Ko, Sumanth Katte Gururajarao, Hugh Mair, Peter Cumming, Franck Dahan | 2006-01-24 |
| 6956398 | Leakage current reduction method | Hugh Mair, Luan Dang, Xiaowei Deng, George B. Jamison, Tam Minh Dai Tran +1 more | 2005-10-18 |