Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12094880 | Integrated circuits and manufacturing methods thereof | Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin +6 more | 2024-09-17 |
| 12008302 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Yuan-Te Hou, Chung-Hsing Wang | 2024-06-11 |
| 11682665 | Semiconductor layout with different row heights | Hui-Zhong Zhuang, Xiang-Dong Chen, Lee-Chung Lu, Tzu-Ying Lin | 2023-06-20 |
| 11593546 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Yuan-Te Hou, Chung-Hsing Wang | 2023-02-28 |
| 11581314 | Integrated circuits and manufacturing methods thereof | Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin +6 more | 2023-02-14 |
| 11113443 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Yuan-Te Hou, Chung-Hsing Wang | 2021-09-07 |
| 11017149 | Machine-learning design enablement platform | Yi-Lin Chuang, Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yun-Han Lee | 2021-05-25 |
| 10678973 | Machine-learning design enablement platform | Yi-Lin Chuang, Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yun-Han Lee | 2020-06-09 |
| 10535655 | Integrated circuits and manufacturing methods thereof | Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin +6 more | 2020-01-14 |
| 9811627 | Method of component partitions on system on chip and device thereof | Sandeep Kumar Goel, Yun-Han Lee | 2017-11-07 |
| 9312260 | Integrated circuits and manufacturing methods thereof | Ali Keshavarzi, Ta-Pen Guo, Helen Shu-Hui Chang, Hsiang-Jen Tseng, Shyue-Shyh Lin +6 more | 2016-04-12 |
| 8671367 | Integrated circuit design in optical shrink technology node | Chung-Hsing Wang, Lee-Chung Lu, Lie-Szu Juang | 2014-03-11 |
| 8671382 | Method of generating RC technology file | Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng | 2014-03-11 |
| 8631366 | Integrated circuit design using DFM-enhanced architecture | Lee-Chung Lu, Li-Chun Tien, Yi-Kan Cheng, Chun-Hui Tai, Ta-Pen Guo +1 more | 2014-01-14 |
| 8507957 | Integrated circuit layouts with power rails under bottom metal layer | Shyue-Shyh Lin, Li-Chun Tien, Shu-Min Chen, Pin-Dai Sue | 2013-08-13 |
| 8504965 | Method for non-shrinkable IP integration | Hung-Yi Liu, Chung-Hsing Wang, Lie-Szu Juang | 2013-08-06 |
| 8504972 | Standard cells having flexible layout architecture/boundaries | David B. Scott, Lee-Chung Lu, Li-Chun Tien | 2013-08-06 |
| 8431985 | Layout and process of forming contact plugs | Lee-Chung Lu, Shyue-Shyh Lin, Li-Chun Tien | 2013-04-30 |
| 8418112 | Method of generating RC technology file | Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng | 2013-04-09 |
| 8261219 | System on chip development with reconfigurable multi-project wafer technology | Kun-Lung Chen, Shine C. Chung, Yu-Chun Wu | 2012-09-04 |
| 8255837 | Methods for cell boundary isolation in double patterning design | Lee-Chung Lu, Yi-Kan Cheng, Yuan-Te Hou, Li-Chun Tien | 2012-08-28 |
| 8217469 | Contact implement structure for high density design | Yuh-Jier Mii, Kuo-Tung Sung, Li-Chun Tien | 2012-07-10 |
| 8201111 | Table-based DFM for accurate post-layout analysis | Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin +5 more | 2012-06-12 |
| 8001494 | Table-based DFM for accurate post-layout analysis | Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin +5 more | 2011-08-16 |
| 7932566 | Structure and system of mixing poly pitch cell design under default poly pitch design rules | Li-Chun Tien, Lee-Chung Lu, Ping Li, Ta-Pen Guo | 2011-04-26 |