Issued Patents All Time
Showing 1–25 of 391 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12374829 | Circuit board module and release component | Yung-Shun Kao | 2025-07-29 |
| 12341103 | Integrated circuit and method of manufacturing same | Pochun Wang, Ting-Wei Chiang, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu +6 more | 2025-06-24 |
| 12336296 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Jiann-Tyng Tzeng, Shun Li Chen, Kam-Tou Sio +3 more | 2025-06-17 |
| 12278230 | Method of manufacturing conductors for semiconductor device | Kam-Tou Sio, Chih-Liang Chen, Hui-Ting Yang, Shun Li Chen, Ko-Bin Kao +2 more | 2025-04-15 |
| 12266539 | Method of manufacturing semiconductor devices | Ru-Gun Liu, Wei-Liang Lin, Yung-Sung Yen, Ken-Hsien Hsieh, Chin-Hsiang Lin | 2025-04-01 |
| 12160968 | Remote releasing module and circuit board device | Yung-Shun Kao | 2024-12-03 |
| 12148653 | Method of manufacturing semiconductor devices | Ru-Gun Liu, Chin-Hsiang Lin, Wei-Liang Lin, Yung-Sung Yen | 2024-11-19 |
| 12142342 | Memory circuit with sense amplifier calibration mechanism | Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin | 2024-11-12 |
| 12125712 | Landing metal etch process for improved overlay control | Chih-Min HSIAO, Chien-Wen Lai, Ya Hui Chang, Ru-Gun Liu | 2024-10-22 |
| 12125850 | Buried metal track and methods forming same | Pochun Wang, Ting-Wei Chiang, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu +6 more | 2024-10-22 |
| 12113132 | Metal rail conductors for non-planar semiconductor devices | Chih-Liang Chen, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Chiang +5 more | 2024-10-08 |
| 12080588 | Buried metal for FinFET device and method | Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Ru-Gun Liu, Charles Chew-Yuen Young | 2024-09-03 |
| 12062543 | Line-end extension method and device | Chih-Min HSIAO, Chien-Wen Lai, Ru-Gun Liu, Shih-Ming Chang, Yung-Sung Yen +1 more | 2024-08-13 |
| 12014926 | Self aligned litho etch process patterning method | Chih-Min HSIAO, Chien-Wen Lai, Shih-Chun Huang, Yung-Sung Yen, Ru-Gun Liu | 2024-06-18 |
| 11935825 | Contact structure, method, layout, and system | Kam-Tou Sio, Cheng-Chi Chuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan | 2024-03-19 |
| 11929258 | Via connection to a partially filled trench | Shih-Ming Chang, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao +1 more | 2024-03-12 |
| 11917762 | Circuit board module | Yung-Shun Kao | 2024-02-27 |
| 11916077 | Method for routing local interconnect structure at same level as reference metal line | Chih-Liang Chen, Cheng-Chi Chuang, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang +5 more | 2024-02-27 |
| 11901190 | Method of patterning | Chin-Yuan Tseng, Yu-Tien Shen, Wei-Liang Lin, Kuo-Cheng Ching, Shi Ning Ju +2 more | 2024-02-13 |
| 11862623 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Jiann-Tyng Tzeng, Shun Li Chen, Kam-Tou Sio +3 more | 2024-01-02 |
| 11854807 | Line-end extension method and device | Chih-Min HSIAO, Chien-Wen Lai, Ru-Gun Liu, Shih-Ming Chang, Yung-Sung Yen +1 more | 2023-12-26 |
| 11854820 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chia-Ying Lee, Jyu-Horng Shieh +6 more | 2023-12-26 |
| 11848208 | Method for forming semiconductor device structure | Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu | 2023-12-19 |
| 11841619 | Method for mask data synthesis with wafer target adjustment | Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Jue-Chin Yu, Ru-Gun Liu +1 more | 2023-12-12 |
| 11810811 | Buried metal for FinFET device and method | Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Ru-Gun Liu, Charles Chew-Yuen Young | 2023-11-07 |