Issued Patents All Time
Showing 1–25 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424488 | Dual etch-stop layer structure | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu | 2025-09-23 |
| 12406924 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao | 2025-09-02 |
| 12394633 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2025-08-19 |
| 12368046 | Method and structure of cut end with self-aligned double patterning | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2025-07-22 |
| 12362231 | Self-assembled dielectric on metal rie lines to increase reliability | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao | 2025-07-15 |
| 12354881 | Methods of etching metals in semiconductor devices | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2025-07-08 |
| 12322723 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2025-06-03 |
| 12315817 | Dielectric on wire structure to increase processing window for overlying via | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2025-05-27 |
| 12310255 | Structure and method for an MRAM device with a multi-layer top electrode | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2025-05-20 |
| 12308238 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao | 2025-05-20 |
| 12302761 | Magnetic tunnel junction devices | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2025-05-13 |
| 12300600 | Semiconductor device with self-aligned conductive features | Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu | 2025-05-13 |
| 12300611 | Interconnect conductive structure comprising two conductive materials | Yu-Teng Dai, Hsi-Wen Tien, Wei-Hao Liao, Hsin-Chieh Yao, Chih Wei Lu | 2025-05-13 |
| 12266565 | Integrated chip with an etch-stop layer forming a cavity | Hsi-Wen Tien, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai +1 more | 2025-04-01 |
| 12261121 | Structure and method for a low-k dielectric with pillar-type air-gaps | Chih Wei Lu, Tien-I Bao | 2025-03-25 |
| 12243775 | Double patterning approach by direct metal etch | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu | 2025-03-04 |
| 12165920 | Semiconductor structure and method for forming the same | Hwei-Jay CHU, Chieh-Han Wu, Cheng-Hsiung Tsai | 2024-12-10 |
| 12125795 | Integrated chip with inter-wire cavities | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai +2 more | 2024-10-22 |
| 12094823 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao | 2024-09-17 |
| 12074059 | Semiconductor arrangement and method of making | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2024-08-27 |
| 12046551 | Interconnect structure having a barrier layer along the sidewall of self-aligned via structures | Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu | 2024-07-23 |
| 11972975 | Semiconductor device structure having air gap and method for forming the same | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu +1 more | 2024-04-30 |
| 11955376 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Tien-I Bao | 2024-04-09 |
| 11942364 | Selective deposition of a protective layer to reduce interconnect structure critical dimensions | Hsi-Wen Tien, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao | 2024-03-26 |
| 11929258 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Tien-I Bao +1 more | 2024-03-12 |