Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12342727 | Magnetoresistive random-access memory (MRAM) structure for improving process control and method of fabricating thereof | Hsiang-Lun Kao, Chen-Chiu Huang, Chung-Te Lin | 2025-06-24 |
| 12324164 | Alignment mark for MRAM device and method | Wei-De Ho, Lan-Hsin Chiang, Chung-Te Lin, Yung-Yu Wang, Sheng-Yuan Chang +1 more | 2025-06-03 |
| 12308238 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao | 2025-05-20 |
| 12262642 | Method of fabricating magneto-resistive random access memory (MRAM) | Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin | 2025-03-25 |
| 12245515 | Interconnection for a memory array and methods for forming the same | Yu-Feng Yin, Min Dai, Chung-Te Lin | 2025-03-04 |
| 12211700 | Selective removal of an etching stop layer for improving overlay shift tolerance | Tzu-Hui Wei, Cherng-Shiaw Tsai | 2025-01-28 |
| 12048250 | Method of fabricating magneto-resistive random access memory (MRAM) | Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin | 2024-07-23 |
| 12010924 | Method for manufacturing semiconductor structure with memory device | Chih-Pin Chiu, Chang-Lin Yang, Chen-Chiu Huang, Chih-Fan Huang, Dian-Hau Chen | 2024-06-11 |
| 11856854 | MRAM device structures and method of fabricating the same | Yu-Feng Yin, Min Dai, Chung-Te Lin | 2023-12-26 |
| 11849644 | Method of fabricating magneto-resistive random access memory (MRAM) | Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin | 2023-12-19 |
| 11664237 | Semiconductor device having improved overlay shift tolerance | Tzu-Hui Wei, Cherng-Shiaw Tsai | 2023-05-30 |
| 11495465 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao | 2022-11-08 |
| 11211549 | Integrated circuit and method for manufacturing the same | Chang-Lin Yang, Chung-Te Lin, Han-Ting Tsai | 2021-12-28 |
| 11011421 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2021-05-18 |
| 10998225 | Semiconductor device and method of forming the same | Tzu-Hui Wei, Cherng-Shiaw Tsai, Chung-Ju Lee | 2021-05-04 |
| 10867805 | Selective removal of an etching stop layer for improving overlay shift tolerance | Tzu-Hui Wei, Cherng-Shiaw Tsai | 2020-12-15 |
| 10854458 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao | 2020-12-01 |
| 10784160 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2020-09-22 |
| 10515945 | Method and structure for semiconductor mid-end-of-year (MEOL) process | Chih Wei Lu, Chung-Ju Lee, Hsiang-Ku Shen, Zhao-Cheng Chen | 2019-12-24 |
| 10269634 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2019-04-23 |
| 10163887 | Method and structure for semiconductor mid-end-of-line (MEOL) process | Chih Wei Lu, Chung-Ju Lee, Hsiang-Ku Shen, Zhao-Cheng Chen | 2018-12-25 |
| 10068770 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao | 2018-09-04 |
| 10032640 | Formation of semiconductor structure with a photoresist cross link and de-cross link process | Chung-Ju Lee, Ming-Hui Weng, Tzu-Hui Wei | 2018-07-24 |
| 10002820 | Through silicon via layout pattern | Sun-Rong Jan, Che-Yu Yeh, Chee-Wee Liu, Bing J. Sheu | 2018-06-19 |
| 9947646 | Method and structure for semiconductor mid-end-of-line (MEOL) process | Chih Wei Lu, Chung-Ju Lee, Hsiang-Ku Shen, Zhao-Cheng Chen | 2018-04-17 |