Issued Patents All Time
Showing 1–25 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412831 | Semiconductor device structure and methods of forming the same | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Cherng-Shiaw Tsai, Chia-Wei Su | 2025-09-09 |
| 12394633 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2025-08-19 |
| 12300600 | Semiconductor device with self-aligned conductive features | Tai-I Yang, Wei-Chen Chu, Chung-Ju Lee | 2025-05-13 |
| 12080593 | Barrier-less structures | Hsin-Ping Chen, Ming-Han Lee, Shin-Yi Yang, Chia-Tien Wu, Shau-Lin Shue +1 more | 2024-09-03 |
| 12062611 | Integrated circuit interconnect structures with air gaps | Tai-I Yang, Li-Lin Su, Hsin-Ping Chen, Cheng-Chi Chuang | 2024-08-13 |
| 12009202 | Using a self-assembly layer to facilitate selective formation of an etching stop layer | Shao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue | 2024-06-11 |
| 11894238 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2024-02-06 |
| 11860550 | Multi-metal fill with self-aligned patterning and dielectric with voids | Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su | 2024-01-02 |
| 11848190 | Barrier-less structures | Hsin-Ping Chen, Chia-Tien Wu, Min Cao, Ming-Han Lee, Shau-Lin Shue +1 more | 2023-12-19 |
| 11532552 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao | 2022-12-20 |
| 11422475 | Multi-metal fill with self-aligned patterning and dielectric with voids | Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su | 2022-08-23 |
| 11404367 | Method for forming semiconductor device with self-aligned conductive features | Tai-I Yang, Wei-Chen Chu, Chung-Ju Lee | 2022-08-02 |
| 11387113 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2022-07-12 |
| 11244898 | Integrated circuit interconnect structures with air gaps | Tai-I Yang, Li-Lin Su, Hsin-Ping Chen, Cheng-Chi Chuang | 2022-02-08 |
| 11069526 | Using a self-assembly layer to facilitate selective formation of an etching stop layer | Shao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue | 2021-07-20 |
| 11011421 | Semiconductor device having voids and method of forming same | Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2021-05-18 |
| 10916443 | Spacer-damage-free etching | Tsung-Min Huang, Chung-Ju Lee | 2021-02-09 |
| 10867913 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao | 2020-12-15 |
| 10818509 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2020-10-27 |
| 10784160 | Semiconductor device having voids and method of forming same | Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2020-09-22 |
| 10714421 | Structure and formation method of semiconductor device with self-aligned conductive features | Tai-I Yang, Wei-Chen Chu, Chung-Ju Lee | 2020-07-14 |
| 10534273 | Multi-metal fill with self-aligned patterning and dielectric with voids | Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su | 2020-01-14 |
| 10283371 | Spacer-damage-free etching | Tsung-Min Huang, Chung-Ju Lee | 2019-05-07 |
| 10269634 | Semiconductor device having voids and method of forming same | Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2019-04-23 |
| 10170306 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Shau-Lin Shue, Tien-I Bao | 2019-01-01 |