Issued Patents All Time
Showing 1–25 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424488 | Dual etch-stop layer structure | Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee | 2025-09-23 |
| 12412831 | Semiconductor device structure and methods of forming the same | Wei-Hao Liao, Chih Wei Lu, Yung-Hsu Wu, Cherng-Shiaw Tsai, Chia-Wei Su | 2025-09-09 |
| 12406924 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Chung-Ju Lee | 2025-09-02 |
| 12368046 | Method and structure of cut end with self-aligned double patterning | Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2025-07-22 |
| 12362231 | Self-assembled dielectric on metal rie lines to increase reliability | Wei-Hao Liao, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2025-07-15 |
| 12354881 | Methods of etching metals in semiconductor devices | Wei-Hao Liao, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2025-07-08 |
| 12322723 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Yu-Teng Dai, Wei-Hao Liao | 2025-06-03 |
| 12315817 | Dielectric on wire structure to increase processing window for overlying via | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Yu-Teng Dai, Wei-Hao Liao | 2025-05-27 |
| 12310255 | Structure and method for an MRAM device with a multi-layer top electrode | Wei-Hao Liao, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2025-05-20 |
| 12300541 | Structure and formation method of semiconductor device with carbon-containing conductive structure | Wei-Hao Liao, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Hwei-Jay CHU | 2025-05-13 |
| 12300611 | Interconnect conductive structure comprising two conductive materials | Yu-Teng Dai, Wei-Hao Liao, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee | 2025-05-13 |
| 12302761 | Magnetic tunnel junction devices | Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2025-05-13 |
| 12266565 | Integrated chip with an etch-stop layer forming a cavity | Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai +1 more | 2025-04-01 |
| 12243775 | Double patterning approach by direct metal etch | Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee | 2025-03-04 |
| 12125795 | Integrated chip with inter-wire cavities | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Wei-Hao Liao, Yu-Teng Dai +2 more | 2024-10-22 |
| 12094823 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Chung-Ju Lee | 2024-09-17 |
| 12074059 | Semiconductor arrangement and method of making | Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2024-08-27 |
| 11972975 | Semiconductor device structure having air gap and method for forming the same | Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee +1 more | 2024-04-30 |
| 11942364 | Selective deposition of a protective layer to reduce interconnect structure critical dimensions | Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao | 2024-03-26 |
| 11923293 | Barrier structure on interconnect wire to increase processing window for overlying via | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Wei-Hao Liao, Yu-Teng Dai | 2024-03-05 |
| 11915943 | Methods of etching metals in semiconductor devices | Wei-Hao Liao, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2024-02-27 |
| 11856866 | Magnetic tunnel junction devices | Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2023-12-26 |
| 11854836 | Semiconductor device | Wei-Hao Liao, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2023-12-26 |
| 11854965 | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability | Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Wei-Hao Liao | 2023-12-26 |
| 11848207 | Method and structure of cut end with self-aligned double patterning | Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2023-12-19 |