Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163654 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2018-12-25 |
| 10014175 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2018-07-03 |
| 9997404 | Method of forming an interconnect structure for a semiconductor device | Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee, Yung-Sung Yen +4 more | 2018-06-12 |
| 9947535 | Trench formation using horn shaped spacer | Tsung-Min Huang, Chung-Ju Lee | 2018-04-17 |
| 9922927 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao | 2018-03-20 |
| 9911646 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2018-03-06 |
| 9831117 | Self-aligned double spacer patterning process | Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2017-11-28 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2017-09-26 |
| 9735052 | Metal lines for interconnect structure and method of manufacturing same | Cheng-Hsiung Tsai, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao +1 more | 2017-08-15 |
| 9659864 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao | 2017-05-23 |
| 9627206 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Shau-Lin Shue, Tien-I Bao | 2017-04-18 |
| 9607850 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2017-03-28 |
| 9601346 | Spacer-damage-free etching | Tsung-Min Huang, Chung-Ju Lee | 2017-03-21 |
| 9589890 | Method for interconnect scheme | Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang +3 more | 2017-03-07 |
| 9576896 | Semiconductor arrangement and formation thereof | Yu-Chieh Liao, Cheng-Chi Chuang, Tai-I Yang, Tien-Lu Lin | 2017-02-21 |
| 9514979 | Trench formation using horn shaped spacer | Tsung-Min Huang, Chung-Ju Lee | 2016-12-06 |
| 9490136 | Method of forming trench cut | Yu-Sheng Chang, Chia-Tien Wu | 2016-11-08 |
| 9431297 | Method of forming an interconnect structure for a semiconductor device | Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee, Yung-Sung Yen +4 more | 2016-08-30 |
| 9418868 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2016-08-16 |
| 9412649 | Method of fabricating semiconductor device | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2016-08-09 |
| 9349690 | Semiconductor arrangement and formation thereof | Yu-Chieh Liao, Cheng-Chi Chuang, Tai-I Yang, Tien-Lu Lin | 2016-05-24 |
| 9330989 | System and method for chemical-mechanical planarization of a metal layer | Shih-Kang Fu, Hsin-Chieh Yao, Hsiang-Huan Lee, Chung-Ju Lee, Hai-Ching Chen +1 more | 2016-05-03 |
| 9209076 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Hsin-Chieh Yao, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2015-12-08 |
| 9177797 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Chung-Ju Lee, Cheng-Hsiung Tsai, Hsiang-Huan Lee, Hai-Ching Chen +5 more | 2015-11-03 |
| 9136162 | Trench formation using horn shaped spacer | Tsung-Min Huang, Chung-Ju Lee | 2015-09-15 |