Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12191239 | Stacked via structure disposed on a conductive pillar of a semiconductor die | Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng | 2025-01-07 |
| 11756870 | Stacked via structure disposed on a conductive pillar of a semiconductor die | Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng | 2023-09-12 |
| 10213986 | Electric connection and method of manufacturing the same | Shih-Kang Lin, Hao-Miao Chang, Mei-Jun Wang, Cheng-Liang Cho | 2019-02-26 |
| 10002820 | Through silicon via layout pattern | Sun-Rong Jan, Chee-Wee Liu, Chien-Hua Huang, Bing J. Sheu | 2018-06-19 |
| 9997615 | Method for forming semiconductor structure with epitaxial growth structure | Chung-Cheng Wu, Cheng-Long Chen, Gwan Sin Chang, Pang-Yen Tsai, Yen-Ming Chen +2 more | 2018-06-12 |