Issued Patents All Time
Showing 26–50 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11923293 | Barrier structure on interconnect wire to increase processing window for overlying via | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai | 2024-03-05 |
| 11915943 | Methods of etching metals in semiconductor devices | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2024-02-27 |
| 11894238 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2024-02-06 |
| 11856866 | Magnetic tunnel junction devices | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2023-12-26 |
| 11854965 | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability | Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao | 2023-12-26 |
| 11854820 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh +6 more | 2023-12-26 |
| 11854836 | Semiconductor device | Hsi-Wen Tien, Wei-Hao Liao, Chih Wei Lu, Pin-Ren Dai | 2023-12-26 |
| 11849645 | Integrated circuit | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2023-12-19 |
| 11848207 | Method and structure of cut end with self-aligned double patterning | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2023-12-19 |
| 11842924 | Dual etch-stop layer structure | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu | 2023-12-12 |
| 11842966 | Integrated chip with inter-wire cavities | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai +2 more | 2023-12-12 |
| 11837546 | Self-aligned cavity strucutre | Wei-Hao Liao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2023-12-05 |
| 11830910 | Semiconductor structure having air gaps and method for manufacturing the same | Chieh-Han Wu, Hwei-Jay CHU, An-Dih Yu, Tzu-Hui Wei, Cheng-Hsiung Tsai +2 more | 2023-11-28 |
| 11798910 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2023-10-24 |
| 11798840 | Self-assembled dielectric on metal RIE lines to increase reliability | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao | 2023-10-24 |
| 11776845 | Semiconductor arrangement and method of making | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2023-10-03 |
| 11756884 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao | 2023-09-12 |
| 11728271 | Structure and method for a low-K dielectric with pillar-type air-gaps | Chih Wei Lu, Tien-I Bao | 2023-08-15 |
| 11723282 | Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2023-08-08 |
| 11688782 | Semiconductor structure and method for forming the same | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao | 2023-06-27 |
| 11676862 | Semiconductor device structure and methods of forming the same | Hwei-Jay CHU, Chieh-Han Wu, Hsin-Chieh Yao, Cheng-Hsiung Tsai | 2023-06-13 |
| 11652054 | Dielectric on wire structure to increase processing window for overlying via | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2023-05-16 |
| 11631639 | Method of fabricating self-aligned via structures | Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu | 2023-04-18 |
| 11569127 | Double patterning approach by direct metal etch | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu | 2023-01-31 |
| 11569124 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Shau-Lin Shue, Tien-I Bao | 2023-01-31 |