Issued Patents All Time
Showing 51–75 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11569096 | Semiconductor device | Hsi-Wen Tien, Wei-Hao Liao, Chih Wei Lu, Pin-Ren Dai | 2023-01-31 |
| 11563167 | Structure and method for an MRAM device with a multi-layer top electrode | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2023-01-24 |
| 11532547 | Interconnect structures with low-aspect-ratio contact vias | Cheng-Hsiung Tsai, Ming-Han Lee | 2022-12-20 |
| 11521896 | Selective deposition of a protective layer to reduce interconnect structure critical dimensions | Hsi-Wen Tien, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao | 2022-12-06 |
| 11495465 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao | 2022-11-08 |
| 11488926 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2022-11-01 |
| 11482447 | Method of forming an integrated chip having a cavity between metal features | Hsi-Wen Tien, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai +1 more | 2022-10-25 |
| 11404367 | Method for forming semiconductor device with self-aligned conductive features | Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu | 2022-08-02 |
| 11393718 | Semiconductor structure and method for forming the same | Hwei-Jay CHU, Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu | 2022-07-19 |
| 11387113 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2022-07-12 |
| 11362030 | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability | Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao | 2022-06-14 |
| 11355701 | Integrated circuit | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2022-06-07 |
| 11329216 | Magnetic tunnel junction devices | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2022-05-10 |
| 11302641 | Self-aligned cavity strucutre | Wei-Hao Liao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2022-04-12 |
| 11251118 | Self-aligned via structures with barrier layers | Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu | 2022-02-15 |
| 11189524 | Semiconductor arrangement and method of making | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2021-11-30 |
| 11183422 | Semiconductor structure and method for manufacturing the same | Tai-I Yang, Wei-Chen Chu, Hsin-Ping Chen, Chih Wei Lu | 2021-11-23 |
| 11171052 | Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2021-11-09 |
| 11171284 | Memory device | Wei-Hao Liao, Chih Wei Lu, Hsi-Wen Tien, Pin-Ren Dai | 2021-11-09 |
| 11171041 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Tien-I Bao | 2021-11-09 |
| 11158518 | Methods of etching metals in semiconductor devices | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2021-10-26 |
| 11139236 | Semiconductor devices and methods of forming the same | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Hsin-Chieh Yao, Chih Wei Lu | 2021-10-05 |
| 11087994 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Tien-I Bao +1 more | 2021-08-10 |
| 11063213 | Method for manufacturing memory device | Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, David Dai | 2021-07-13 |
| 11050018 | Memory device | Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, David Dai | 2021-06-29 |