Issued Patents All Time
Showing 101–125 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10629479 | Structure and method for interconnection | Chih Wei Lu, Tien-I Bao | 2020-04-21 |
| 10622551 | Manufacturing techniques and devices for magnetic tunnel junction devices | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2020-04-14 |
| 10515945 | Method and structure for semiconductor mid-end-of-year (MEOL) process | Chih Wei Lu, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen | 2019-12-24 |
| 10515823 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Tien-I Bao +1 more | 2019-12-24 |
| 10505018 | Spacers with rectangular profile and methods of forming the same | Yu-Sheng Chang, Tien-I Bao | 2019-12-10 |
| 10461246 | Memory device and method for manufacturing the same | Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, David Dai | 2019-10-29 |
| 10355198 | Memory device and fabrication method thereof | Wei-Hao Liao, Chih Wei Lu, Hsi-Wen Tien, Pin-Ren Dai | 2019-07-16 |
| 10354954 | Copper etching integration scheme | Chih Wei Lu, Hsiang-Huan Lee, Tien-I Bao | 2019-07-16 |
| 10340181 | Interconnect structure including air gap | Tai-I Yang, Wei-Chen Chu, Hsin-Ping Chen, Chih Wei Lu | 2019-07-02 |
| 10312139 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Shau-Lin Shue, Tien-I Bao | 2019-06-04 |
| 10312136 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Tien-I Bao | 2019-06-04 |
| 10290536 | Structure and method for interconnection | Chih Wei Lu, Tien-I Bao | 2019-05-14 |
| 10283371 | Spacer-damage-free etching | Tsung-Min Huang, Yung-Hsu Wu | 2019-05-07 |
| 10269634 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chien-Hua Huang, Tien-I Bao, Shau-Lin Shue | 2019-04-23 |
| 10270028 | Memory device and method for manufacturing the same | Hsi-Wen Tien, Chih Wei Lu, Wei-Hao Liao, Pin-Ren Dai | 2019-04-23 |
| 10186455 | Interconnect structure and methods of making same | Tsung-Min Huang, Tsung-Jung Tsai | 2019-01-22 |
| 10170306 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Hsin-Chieh Yao, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu | 2019-01-01 |
| 10163887 | Method and structure for semiconductor mid-end-of-line (MEOL) process | Chih Wei Lu, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen | 2018-12-25 |
| 10163654 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2018-12-25 |
| 10068770 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao | 2018-09-04 |
| 10049919 | Semiconductor device including a target integrated circuit pattern | Chieh-Han Wu, Cheng-Hsiung Tsai, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue +1 more | 2018-08-14 |
| 10049878 | Self-aligned patterning process | Tsung-Min Huang | 2018-08-14 |
| 10032640 | Formation of semiconductor structure with a photoresist cross link and de-cross link process | Chien-Hua Huang, Ming-Hui Weng, Tzu-Hui Wei | 2018-07-24 |
| 10020259 | Copper etching integration scheme | Chih Wei Lu, Hsiang-Huan Lee, Tien-I Bao | 2018-07-10 |
| 10014175 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh +5 more | 2018-07-03 |