Issued Patents All Time
Showing 1–25 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12292694 | Alignment mark and method | Hung-Chung Chien, Chih-Chieh Yang, Hao-Ken HUNG | 2025-05-06 |
| 12218239 | Structure and method for providing line end extensions for fin-type active regions | Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang +2 more | 2025-02-04 |
| 12165923 | Method of manufacturing a semiconductor device | Chuan-Hui Lu, Ming-Jhih Kuo, Ming-Wen HSIAO | 2024-12-10 |
| 12165973 | Semiconductor device with backside power rail and method for forming the same | Hung-Chung Chien, Chao-Hong Chen | 2024-12-10 |
| 11876054 | Overlay mark and method of making | Chen Chen, Ching-Yu Chang | 2024-01-16 |
| 11862690 | Method of manufacturing a semiconductor device | Ming-Wen HSIAO, Chun-Yen Tai, Yen-Hsin Liu, Ming-Jhih Kuo | 2024-01-02 |
| 11854820 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2023-12-26 |
| 11735477 | Method of semiconductor integrated circuit fabrication | Hung-Chang Hsieh, Wen-Hung Tseng | 2023-08-22 |
| 11721761 | Structure and method for providing line end extensions for fin-type active regions | Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang +2 more | 2023-08-08 |
| 11387105 | Loading effect reduction through multiple coat-etch processes | Jin-Dah Chen, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen | 2022-07-12 |
| 11287746 | System and method for overlay error reduction | Hung-Chung Chien, Hao-Ken HUNG, Chih-Chieh Yang, Chun-Ming Hu | 2022-03-29 |
| 11239365 | Structure and method for providing line end extensions for fin-type active regions | Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang +2 more | 2022-02-01 |
| 11081394 | Method of making a FinFET device | Wen-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh | 2021-08-03 |
| 11037882 | Overlay mark | Chen Chen, Ching-Yu Chang | 2021-06-15 |
| 10770303 | Mechanisms for forming patterns using multiple lithography processes | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau | 2020-09-08 |
| 10755936 | Loading effect reduction through multiple coat-etch processes | Jin-Dah Chen, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen | 2020-08-25 |
| 10672656 | Method of semiconductor integrated circuit fabrication | Hung-Chang Hsieh, Wen-Hung Tseng | 2020-06-02 |
| 10665467 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2020-05-26 |
| 10573751 | Structure and method for providing line end extensions for fin-type active regions | Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang +2 more | 2020-02-25 |
| 10535646 | Systems and methods for a sequential spacer scheme | Shih-Ming Chang, Ru-Gun Liu, Tsai-Sheng Gau | 2020-01-14 |
| 10424543 | Overlay mark | Chen Chen, Ching-Yu Chang | 2019-09-24 |
| 10410913 | Multi-layer metal contacts | Wen-Hung Tseng, Chih-Ming Lai, Ken-Hsien Hsieh, Tsai-Sheng Gau, Ru-Gun Liu | 2019-09-10 |
| 10276392 | Loading effect reduction through multiple coat-etch processes | Jin-Dah Chen, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen | 2019-04-30 |
| 10276363 | Mechanisms for forming patterns using multiple lithography processes | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau | 2019-04-30 |
| 10249570 | Overlay mark | Chen Chen, Ching-Yu Chang | 2019-04-02 |