Issued Patents All Time
Showing 1–25 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406878 | Integrated circuit with conductive line having line-ends | Chih-Yuan Ting, Pei-Wen Huang | 2025-09-02 |
| 12341057 | Interconnect line for semiconductor device | Chung-Wen Wu, Chih-Yuan Ting | 2025-06-24 |
| 12317751 | Integrated circuit | Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang +3 more | 2025-05-27 |
| 12310077 | Dual damascene structure in forming source/drain contacts | Chien-Han Chen, Shih-Yu Chang, Chien-Chih Chiu, Huang-Ming Chen | 2025-05-20 |
| 12237214 | Method of forming a semiconductor device | Yi-Nien Su, Shu-Huei Suen, Ru-Gun Liu | 2025-02-25 |
| 12218007 | Self-aligned via formation using spacers | Yi-Nien Su | 2025-02-04 |
| 12219879 | Gradient protection layer in MTJ manufacturing | Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien-Chung Huang +2 more | 2025-02-04 |
| 12217936 | DC bias in plasma process | Sheng-Liang Pan, Bing Chen, Chia-Yang Hung, Shu-Huei Suen, Syun-Ming Jang +1 more | 2025-02-04 |
| 12183628 | Integrated circuit and method for manufacturing the same | Kuan-Wei Huang, Yi-Nien Su, Yu-Yu Chen | 2024-12-31 |
| 12153350 | Method of manufacturing semiconductor devices | Ru-Gun Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Shu-Huei Suen +7 more | 2024-11-26 |
| 12142520 | Middle-of-line interconnect structure having air gap and method of fabrication thereof | Yi-Nien Su | 2024-11-12 |
| 12127489 | Integrated circuit structure | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2024-10-22 |
| 12068167 | Self-aligned double patterning | Kuan-Wei Huang, Yu-Yu Chen | 2024-08-20 |
| 11980040 | Semiconductor device with magnetic tunnel junctions | Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Chung-Te Lin | 2024-05-07 |
| 11944017 | Semiconductor structure and manufacturing method of the same | Tai-Yen Peng, Yu-Shu Chen, Chien-Chung Huang, Sin-Yi Yang, Chen-Jung Wang +2 more | 2024-03-26 |
| 11923202 | Double patterning method | Chia-Ying Lee | 2024-03-05 |
| 11856865 | Gradient protection layer in MTJ manufacturing | Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien-Chung Huang +2 more | 2023-12-26 |
| 11854766 | DC bias in plasma process | Sheng-Liang Pan, Bing Chen, Chia-Yang Hung, Shu-Huei Suen, Syun-Ming Jang +1 more | 2023-12-26 |
| 11854820 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2023-12-26 |
| 11800812 | Integrated circuit | Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang +3 more | 2023-10-24 |
| 11796922 | Method of manufacturing semiconductor devices | Ru-Gun Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Shu-Huei Suen +7 more | 2023-10-24 |
| 11784056 | Self-aligned double patterning | Kuan-Wei Huang, Yu-Yu Chen | 2023-10-10 |
| 11735469 | Method of forming a semiconductor device | Yi-Nien Su, Shu-Huei Suen, Ru-Gun Liu | 2023-08-22 |
| 11710657 | Middle-of-line interconnect structure having air gap and method of fabrication thereof | Yi-Nien Su | 2023-07-25 |
| 11683991 | Semiconductor structure and manufacturing method of the same | Tai-Yen Peng, Yu-Shu Chen, Chien-Chung Huang, Sin-Yi Yang, Chen-Jung Wang +2 more | 2023-06-20 |