Issued Patents All Time
Showing 1–25 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406878 | Integrated circuit with conductive line having line-ends | Jyu-Horng Shieh, Pei-Wen Huang | 2025-09-02 |
| 12368076 | Interconnect structure and methods of forming the same | Yu-An Chen, I-Chang Lee | 2025-07-22 |
| 12341057 | Interconnect line for semiconductor device | Chung-Wen Wu, Jyu-Horng Shieh | 2025-06-24 |
| 12317751 | Integrated circuit | Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang +3 more | 2025-05-27 |
| 11996327 | Interconnect structure and methods of forming the same | Yu-An Chen, I-Chang Lee | 2024-05-28 |
| 11980040 | Semiconductor device with magnetic tunnel junctions | Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Jyu-Horng Shieh, Chung-Te Lin | 2024-05-07 |
| 11961761 | Mitigating pattern collapse | Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen | 2024-04-16 |
| 11800812 | Integrated circuit | Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang +3 more | 2023-10-24 |
| 11721624 | Patterning approach for improved via landing profile | Chung-Wen Wu | 2023-08-08 |
| 11682580 | Interconnect structure and method of forming the same | Jeng-Shiou Chen | 2023-06-20 |
| 11665971 | Metal etching stop layer in magnetic tunnel junction memory cells | Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien-Chung Huang +2 more | 2023-05-30 |
| 11398405 | Method and apparatus for back end of line semiconductor device processing | Chung-Wen Wu, Jyu-Horng Shieh | 2022-07-26 |
| 11355642 | Method for manufacturing semiconductor structure | Ju-Wang Hsu, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai | 2022-06-07 |
| 11271150 | Integrated circuit | Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang +3 more | 2022-03-08 |
| 11158509 | Pattern fidelity enhancement with directional patterning technology | Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang +7 more | 2021-10-26 |
| 11127630 | Contact plug without seam hole and methods of forming the same | Jyu-Horng Shieh | 2021-09-21 |
| 11101429 | Metal etching stop layer in magnetic tunnel junction memory cells | Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien-Chung Huang +2 more | 2021-08-24 |
| 11088021 | Interconnect structure and method of forming the same | Jeng-Shiou Chen | 2021-08-10 |
| 11043453 | Method of preventing pattern collapse | Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai, Jyu-Horng Shieh | 2021-06-22 |
| 11037981 | Semiconductor device with magnetic tunnel junctions | Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Jyu-Horng Shieh, Chung-Te Lin | 2021-06-15 |
| 11024515 | Systems and methods for in SITU maintenance of a thin hardmask during an etch process | Chung-Wen Wu | 2021-06-01 |
| 10985054 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Jyu-Horng Shieh, Minghsing Tsai | 2021-04-20 |
| 10950495 | Mitigating pattern collapse | Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen | 2021-03-16 |
| 10923423 | Interconnect structure for semiconductor devices | — | 2021-02-16 |
| 10861788 | Patterning approach for improved via landing profile | Chung-Wen Wu | 2020-12-08 |