Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11355642 | Method for manufacturing semiconductor structure | Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai | 2022-06-07 |
| 10483397 | Fin field effect transistor and method of forming the same | Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai | 2019-11-19 |
| 8927353 | Fin field effect transistor and method of forming the same | Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai | 2015-01-06 |
| 8030214 | Method of fabricating gate structures | Pochi Wu, Ryan Chia-Jen Chen | 2011-10-04 |
| 7875547 | Contact hole structures and contact structures and fabrication methods thereof | Jyu-Horng Shieh, Yi-Nien Su, Peng-Fu Hsu, Hun-Jan Tao | 2011-01-25 |
| 7678655 | Spacer layer etch method providing enhanced microelectronic device performance | Hung-Der Su, Yi-Chun Huang, Shien-Yang Wu, Yung-Shun Chen, Tung-Heng Shie +3 more | 2010-03-16 |
| 7425740 | Method and structure for a 1T-RAM bit cell and macro | Sheng-Da Liu, Hung-Wei Chen, Chang-Yun Chang, Zhong Tang Xuan | 2008-09-16 |
| 7400401 | Measuring low dielectric constant film properties during processing | Jang-Shiang Tsai, Peng-Fu Hsu, Baw-Ching Perng, Jyu-Horng Shieh, Yi-Nien Su +1 more | 2008-07-15 |
| 7378308 | CMOS devices with improved gap-filling | Chih-Hsin Ko, Jyu-Horng Shieh, Baw-Ching Perng, Syun-Ming Jang | 2008-05-27 |
| 7341935 | Alternative interconnect structure for semiconductor devices | Jyu-Horng Shieh, Yi-Chun Huang | 2008-03-11 |
| 7316970 | Method for forming high selectivity protection layer on semiconductor device | Chien-Hao Chen, Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen | 2008-01-08 |
| 7271448 | Multiple gate field effect transistor structure | Jyu-Horng Shieh, Hun-Jan Tao, Chang-Yun Chang, Zhong Tang Xuan, Sheng-Da Liu | 2007-09-18 |
| 7265060 | Bi-level resist structure and fabrication method for contact holes on semiconductor substrates | Ming-Huan Tsai, Hun-Jan Tao, Tsang-Jiuh Wu | 2007-09-04 |
| 7259050 | Semiconductor device and method of making the same | Chien-Hao Chen, Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen | 2007-08-21 |
| 7256498 | Resistance-reduced semiconductor device and methods for fabricating the same | Yi-Chun Huang, Jyu-Horng Shieh | 2007-08-14 |
| 7256137 | Method of forming contact plug on silicide structure | Chii-Ming Wu, Chih-Wei Chang, Shau-Lin Shue, Ming-Huan Tsai | 2007-08-14 |
| 7230270 | Self-aligned double gate device and method for forming same | Hao Chen, Baw-Ching Perng, Fu-Liang Yang | 2007-06-12 |
| 7223647 | Method for forming integrated advanced semiconductor device using sacrificial stress layer | Ming-Huan Tsai, Chien-Hao Chen, Yi-Chun Huang | 2007-05-29 |
| 7179701 | Transistor with high dielectric constant gate and method for forming the same | Jyu-Horng Shieh, Ju-Chien Chiang | 2007-02-20 |
| 7052946 | Method for selectively stressing MOSFETs to improve charge carrier mobility | Chien-Hao Chen, Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen | 2006-05-30 |
| 7008878 | Plasma treatment and etching process for ultra-thin dielectric films | Yuan-Hung Chiu, Hun-Jan Tao | 2006-03-07 |
| 6884736 | Method of forming contact plug on silicide structure | Chii-Ming Wu, Mei-Yun Wang, Chih-Wei Chang, Chin-Hwa Hsieh, Shau-Lin Shue +3 more | 2005-04-26 |
| 6838381 | Methods for improving sheet resistance of silicide layer after removal of etch stop layer | Peng-Fu Hsu, Ming-Huan Tsai, Baw-Ching Perng, Yaun-Hung Chiu | 2005-01-04 |
| 6787455 | Bi-layer photoresist method for forming high resolution semiconductor features | Ming-Huan Tsai, Hun-Jan Tao, Cheng-Ku Chen | 2004-09-07 |
| 6780782 | Bi-level resist structure and fabrication method for contact holes on semiconductor substrates | Ming-Huan Tsai, Hun-Jan Tao, Tsang-Jiuh Wu | 2004-08-24 |