Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11535950 | Electro-plating and apparatus for performing the same | Chen-Yuan Kao, Hung-Wen Su | 2022-12-27 |
| 10985054 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh | 2021-04-20 |
| 10714383 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh | 2020-07-14 |
| 10508356 | Electro-plating and apparatus for performing the same | Chen-Yuan Kao, Hung-Wen Su | 2019-12-17 |
| 10290538 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh | 2019-05-14 |
| 9892960 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh | 2018-02-13 |
| 9518334 | Electro-plating and apparatus for performing the same | Chen-Yuan Kao, Hung-Wen Su | 2016-12-13 |
| 9401329 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh | 2016-07-26 |
| 9214383 | Method of semiconductor integrated circuit fabrication | Wen-Jiun Liu, Chien-An Chen, Ya-Lien Lee, Hung-Wen Su, Syun-Ming Jang | 2015-12-15 |
| 9142450 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh | 2015-09-22 |
| 9029260 | Gap filling method for dual damascene process | Chun-Chieh Lin, Hung-Wen Su, Syun-Ming Jang | 2015-05-12 |
| 8980745 | Interconnect structures and methods of forming same | Szu-Ping Tung, Huang-Yi Huang, Wen-Jiun Liu, Ching-Hua Hsieh | 2015-03-17 |
| 8975187 | Stress-controlled formation of tin hard mask | Rueijer Lin, Chun-Chieh Lin, Hung-Wen Su | 2015-03-10 |
| 8962484 | Method of forming pattern for semiconductor device | Chia-Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh, Syun-Ming Jang | 2015-02-24 |
| 8759975 | Approach for reducing copper line resistivity | Hsien-Ming Lee, Syun-Ming Jang | 2014-06-24 |
| 8692351 | Dummy shoulder structure for line stress reduction | Cheng-Cheng Kuo, Luke Lo, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho +2 more | 2014-04-08 |
| 8623760 | Process for improving copper line cap formation | Chien-Hsueh Shih, Chen-Hua Yu, Ming-Shih Yeh | 2014-01-07 |
| 8563391 | Method for forming MIM capacitor in a copper damascene interconnect | Chun-Hong Chen | 2013-10-22 |
| 8322299 | Cluster processing apparatus for metallization processing in semiconductor manufacturing | Chen-Hua Yu, Yi-Li Hsiao | 2012-12-04 |
| 8242016 | Approach for reducing copper line resistivity | Hsien-Ming Lee, Syun-Ming Jang | 2012-08-14 |
| 8193087 | Process for improving copper line cap formation | Chien-Hsueh Shih, Chen-Hua Yu, Ming-Shih Yeh | 2012-06-05 |
| 7771579 | Electro chemical plating additives for improving stress and leveling effect | Ting-Chu Ko, Chien-Hsueh Shih | 2010-08-10 |
| 7659198 | In-situ deposition for Cu hillock suppression | Chung-Hsien Chen, Chun-Chieh Lin, Shau-Lin Shue | 2010-02-09 |
| 7538434 | Copper interconnection with conductive polymer layer and method of forming the same | Chien-Hsueh Shih, Hung-Wen Su, Shau-Lin Shue | 2009-05-26 |
| 7483258 | MIM capacitor in a copper damascene interconnect | Chun-Hong Chen | 2009-01-27 |