Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12278188 | Different via configurations for different via interface requirements | Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang +3 more | 2025-04-15 |
| 12176435 | Method for forming fin field effect transistor (FinFET) device structure with conductive layer between gate and gate contact | Chao-Hsun Wang, Kuo-Yi Chao, Chen-Yuan Kao, Mei-Yun Wang | 2024-12-24 |
| 12142565 | Different via configurations for different via interface requirements | Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang +3 more | 2024-11-12 |
| 11908697 | Interconnect structure having a carbon-containing barrier layer | Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su | 2024-02-20 |
| 11855154 | Vertical interconnect features and methods of forming | Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang +2 more | 2023-12-26 |
| 11532561 | Different via configurations for different via interface requirements | Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang +3 more | 2022-12-20 |
| 11527411 | Interconnect structure having a carbon-containing barrier layer | Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su | 2022-12-13 |
| 11271112 | Method for forming fin field effect transistor (FINFET) device structure with conductive layer between gate and gate contact | Chao-Hsun Wang, Kuo-Yi Chao, Chen-Yuan Kao, Mei-Yun Wang | 2022-03-08 |
| 11107896 | Vertical interconnect features and methods of forming | Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang +2 more | 2021-08-31 |
| 11062909 | Interconnect structure having a carbon-containing barrier layer | Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su | 2021-07-13 |
| 10867800 | Method of forming an interconnect structure having a carbon-containing barrier layer | Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su | 2020-12-15 |
| 10840105 | Gate structure with insulating structure and method for manufacturing the same | Yu-Hung Lin, Hon-Lin Huang, Shih-Chi Lin, Sheng-Hsuan Lin | 2020-11-17 |
| 10714329 | Pre-clean for contacts | Yu-Ting Lin, Chen-Yuan Kao, Yu-Sheng Wang, I-Li Chen, Hong-Ming Wu | 2020-07-14 |
| 10529575 | Interconnect structure having a carbon-containing barrier layer | Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su | 2020-01-07 |
| 10505045 | Fin field effect transistor (FinFET) device structure with conductive layer between gate and gate contact | Chao-Hsun Wang, Kuo-Yi Chao, Chen-Yuan Kao, Mei-Yun Wang | 2019-12-10 |
| 10312098 | Method of forming an interconnect structure | Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su | 2019-06-04 |
| 10163644 | Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same | Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su | 2018-12-25 |
| 10163719 | Method of forming self-alignment contact | Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Sheng-Hsuan Lin +3 more | 2018-12-25 |
| 10050116 | Semiconductor device structure and method for forming the same | Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Sheng-Hsuan Lin +2 more | 2018-08-14 |
| 9991125 | Method for forming semiconductor device structure | Chen-Yuan Kao, Chun-Chieh Lin, Huang-Yi Huang | 2018-06-05 |
| 9818834 | Semiconductor device structure and method for forming the same | Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Sheng-Hsuan Lin +2 more | 2017-11-14 |
| 9601430 | Semiconductor device structure and method for forming the same | Chen-Yuan Kao, Chun-Chieh Lin, Huang-Yi Huang | 2017-03-21 |
| 9218970 | Stress-controlled formation of TiN hard mask | Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai | 2015-12-22 |
| 8975187 | Stress-controlled formation of tin hard mask | Chun-Chieh Lin, Hung-Wen Su, Minghsing Tsai | 2015-03-10 |