Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12007431 | Test circuit and method for operating the same | Chia-Wei Huang, WEI-JHIH WANG, Yuan-Yao Chang | 2024-06-11 |
| 11990531 | Vertical tunneling field-effect transistor cell | Harry-Hay-Lay Chuang, Ming Zhu | 2024-05-21 |
| 11392745 | Method for improving circuit layout for manufacturability | Yun Wu, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen +2 more | 2022-07-19 |
| 11011621 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Ming Zhu | 2021-05-18 |
| 10853552 | Method for improving circuit layout for manufacturability | Yun Wu, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen +2 more | 2020-12-01 |
| 10490654 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Chi-Wen Liu, Ming Zhu | 2019-11-26 |
| 10424652 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Ming Zhu | 2019-09-24 |
| 10282504 | Method for improving circuit layout for manufacturability | Yun Wu, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen +2 more | 2019-05-07 |
| 10164076 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Chi-Wen Liu, Ming Zhu | 2018-12-25 |
| 10026656 | Metal gate features of semiconductor die | Harry-Hak-Lay Chuang | 2018-07-17 |
| 9853125 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Chi-Wen Liu, Ming Zhu | 2017-12-26 |
| 9806172 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Ming Zhu | 2017-10-31 |
| 9748107 | Method for removing semiconductor fins using alternating masks | Tzu-Chun Lo, Min Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai +3 more | 2017-08-29 |
| 9536867 | N/P boundary effect reduction for metal gate transistors | Hak-Lay Chuang, Ching-Che Tsai, Ming Zhu, Bao-Ru Young | 2017-01-03 |
| 9536977 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Chi-Wen Liu, Ming Zhu | 2017-01-03 |
| 9466714 | Vertical tunneling field-effect transistor cell with coaxially arranged gate contacts and drain contacts | Harry-Hak-Lay Chuang, Ming Zhu | 2016-10-11 |
| 9437485 | Method for line stress reduction through dummy shoulder structures | Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho +2 more | 2016-09-06 |
| 9355209 | Revising layout design through OPC to reduce corner rounding effect | Harry-Hak-Lay Chuang, Ching-Che Tsai, Bao-Ru Young | 2016-05-31 |
| 9190484 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Chi-Wen Liu, Ming Zhu | 2015-11-17 |
| 9184101 | Method for removing semiconductor fins using alternating masks | Tzu-Chun Lo, Min Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai +3 more | 2015-11-10 |
| 9159826 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Ming Zhu | 2015-10-13 |
| 9153581 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Ming Zhu | 2015-10-06 |
| 9123694 | N/P boundary effect reduction for metal gate transistors | Hak-Lay Chuang, Ching-Che Tsai, Ming Zhu, Bao-Ru Young | 2015-09-01 |
| 9070623 | Controlling gate formation for high density cell layout | Harry-Hak-Lay Chuang, Bao-Ru Young, Kuei-Shun Chen, George Liu, Tsung-Chieh Tsai +1 more | 2015-06-30 |
| 9029940 | Vertical tunneling field-effect transistor cell | Harry-Hak-Lay Chuang, Ming Zhu | 2015-05-12 |