Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12349454 | Checkerboard dummy design for epitaxial open ratio | Yu-Chang Jong, Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu, Huan-Chih Yuan +1 more | 2025-07-01 |
| 12322701 | Different scaling ratio in FEOL / MOL/ BEOL | Liang-Yao Lee, Juing-Yi Wu, Chun-Yi Lee | 2025-06-03 |
| 12159870 | Semiconductor structure and forming method thereof | Hung-Shu Huang, Jhih-Bin Chen, Ming Chyi Liu, Yu-Chang Jong, Chien-Chih Chou +3 more | 2024-12-03 |
| 11929288 | Gate-all-around device with different channel semiconductor materials and method of forming the same | Jhe-Ching Lu, Bao-Ru Young, Yen-Sen Wang | 2024-03-12 |
| 11626398 | Semiconductor structure and method for manufacturing thereof | Ta-Wei Lin, Fu-Hsiung Yang, CHING-HSUN HSU, Yu-Lun Lu, Li-Hsuan Yeh +1 more | 2023-04-11 |
| 11508624 | Gate-all-around device with different channel semiconductor materials and method of forming the same | Jhe-Ching Lu, Bao-Ru Young, Yen-Sen Wang | 2022-11-22 |
| 11281835 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Juing-Yi Wu +2 more | 2022-03-22 |
| 11152303 | Different scaling ratio in FEOL / MOL/ BEOL | Liang-Yao Lee, Juing-Yi Wu, Chun-Yi Lee | 2021-10-19 |
| 10998304 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting | 2021-05-04 |
| 10664639 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Juing-Yi Wu +2 more | 2020-05-26 |
| 10366900 | Semiconductor device and manufacturing method thereof | Juing-Yi Wu, Liang-Yao Lee | 2019-07-30 |
| 10325849 | Different scaling ratio in FEOL/ MOL/ BEOL | Liang-Yao Lee, Juing-Yi Wu, Chun-Yi Lee | 2019-06-18 |
| 10283495 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Chun-Yi Lee, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee +1 more | 2019-05-07 |
| 10269785 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting | 2019-04-23 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang +1 more | 2018-06-05 |
| 9984191 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Juing-Yi Wu +2 more | 2018-05-29 |
| 9746783 | Method for preventing photoresist corner rounding effects | Liang-Yao Lee, Jyh-Kang Ting, Juing-Yi Wu | 2017-08-29 |
| 9637818 | Implant region definition | Juing-Yi Wu, Jyh-Kang Ting, Liang-Yao Lee | 2017-05-02 |
| 9508791 | Semiconductor device having a metal gate | Yung-Che Albert Shih, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee | 2016-11-29 |
| 9472501 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting | 2016-10-18 |
| 9437434 | Semiconductor device and fabrication method thereof | Ming-Hsi Yeh, Chun-Yi Lee | 2016-09-06 |
| 9391056 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Tung-Heng Hsieh, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting +1 more | 2016-07-12 |
| 9292649 | Different scaling ratio in FEOL / MOL/ BEOL | Liang-Yao Lee, Juing-Yi Wu, Chun-Yi Lee | 2016-03-22 |
| 9236379 | Semiconductor device and fabrication method thereof | Yung-Che Albert Shih, Jhy-Kang Ting | 2016-01-12 |
| 9230962 | Semiconductor device and fabrication method therefor | Yung-Che Albert Shih, Jhy-Kang Ting | 2016-01-05 |