Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12322701 | Different scaling ratio in FEOL / MOL/ BEOL | Liang-Yao Lee, Tsung-Chieh Tsai, Chun-Yi Lee | 2025-06-03 |
| 11281835 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai +2 more | 2022-03-22 |
| 11152303 | Different scaling ratio in FEOL / MOL/ BEOL | Liang-Yao Lee, Tsung-Chieh Tsai, Chun-Yi Lee | 2021-10-19 |
| 10998304 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Liang-Yao Lee, Jyh-Kang Ting | 2021-05-04 |
| 10664639 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai +2 more | 2020-05-26 |
| 10366900 | Semiconductor device and manufacturing method thereof | Liang-Yao Lee, Tsung-Chieh Tsai | 2019-07-30 |
| 10325849 | Different scaling ratio in FEOL/ MOL/ BEOL | Liang-Yao Lee, Tsung-Chieh Tsai, Chun-Yi Lee | 2019-06-18 |
| 10283495 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Chun-Yi Lee, Jyh-Kang Ting, Liang-Yao Lee, Tung-Heng Hsieh +1 more | 2019-05-07 |
| 10269785 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Liang-Yao Lee, Jyh-Kang Ting | 2019-04-23 |
| 9984191 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai +2 more | 2018-05-29 |
| 9746783 | Method for preventing photoresist corner rounding effects | Liang-Yao Lee, Jyh-Kang Ting, Tsung-Chieh Tsai | 2017-08-29 |
| 9637818 | Implant region definition | Jyh-Kang Ting, Tsung-Chieh Tsai, Liang-Yao Lee | 2017-05-02 |
| 9508791 | Semiconductor device having a metal gate | Tsung-Chieh Tsai, Yung-Che Albert Shih, Jyh-Kang Ting, Liang-Yao Lee | 2016-11-29 |
| 9472501 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Liang-Yao Lee, Jyh-Kang Ting | 2016-10-18 |
| 9391056 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Liang-Yao Lee, Jyh-Kang Ting +1 more | 2016-07-12 |
| 9292649 | Different scaling ratio in FEOL / MOL/ BEOL | Liang-Yao Lee, Tsung-Chieh Tsai, Chun-Yi Lee | 2016-03-22 |
| 9136168 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Liang-Yao Lee, Jyh-Kang Ting | 2015-09-15 |
| 9087773 | Implant region definition | Jyh-Kang Ting, Tsung-Chieh Tsai, Liang-Yao Lee | 2015-07-21 |
| 9047437 | Method, system and software for accessing design rules and library of design features while designing semiconductor device layout | Chin-An Chen, Pei-Tzu Wu, Tsung-Chieh Tsai, Jyh-Kang Ting | 2015-06-02 |
| 8769475 | Method, system and software for accessing design rules and library of design features while designing semiconductor device layout | Chin-An Chen, Pei-Tzu Wu, Tsung-Chieh Tsai, Jyh-Kang Ting | 2014-07-01 |
| 7309897 | Electrostatic discharge protector for an integrated circuit | Kuo-Feng Yu, Jian-Hsing Lee, Chong-Gim Gan, Dun-Nian Yaung | 2007-12-18 |
| 6936408 | Partially photoexposed positive photoresist layer blocking method for regio-selectively processing a microelectronic layer | Yong-Shun Liao, Dian-Hau Chen, Zhen-Cheng Chou | 2005-08-30 |
| 5895257 | LOCOS field oxide and field oxide process using silicon nitride spacers | Chaochieh Tsai, Yuan-Chang Huang, Shun-Liang Hsu | 1999-04-20 |