Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10777534 | Three-dimensional stacking structure | Peter Yu Fei Huang | 2020-09-15 |
| 10157885 | Package structure having magnetic bonding between substrates | Peter Yu Fei Huang, Richard Burton Cassidy, II | 2018-12-18 |
| 9748206 | Three-dimensional stacking structure and manufacturing method thereof | Peter Yu Fei Huang | 2017-08-29 |
| 6943063 | RF seal ring structure | Shyh-Chyi Wong | 2005-09-13 |
| 6737310 | Self-aligned process for a stacked gate RF MOSFET device | Chung-Long Chang, Jui-Yu Chang, Shyh-Chyi Wong | 2004-05-18 |
| 6664635 | Lossless microstrip line in CMOS process | Shyhchyi Wong | 2003-12-16 |
| 6636139 | Structure to reduce the degradation of the Q value of an inductor caused by via resistance | Shyh-Chyi Wong | 2003-10-21 |
| 6495446 | Lossless microstrip line in CMOS process | Shyhchyi Wong | 2002-12-17 |
| 6465367 | Lossless co-planar wave guide in CMOS process | — | 2002-10-15 |
| 6465294 | Self-aligned process for a stacked gate RF MOSFET device | Chung-Long Chang, Ju-Yu Chang, Shyh-Chyi Wong | 2002-10-15 |
| 6444517 | High Q inductor with Cu damascene via/trench etching simultaneous module | Heng-Ming Hsu, Shyh-Chyi Wong, Ssu-Pin Ma, Chao-Cheng Chen, Liang-Kun Huang | 2002-09-03 |
| 6245639 | Method to reduce a reverse narrow channel effect for MOSFET devices | Yuan-Chen Sun | 2001-06-12 |
| 6232164 | Process of making CMOS device structure having an anti-SCE block implant | Kuan-Yao Wang | 2001-05-15 |
| 6175125 | Semiconductor structure for testing vias interconnecting layers of the structure | — | 2001-01-16 |
| 6171913 | Process for manufacturing a single asymmetric pocket implant | Jau-Jey Wang, Jing-Meng Liu | 2001-01-09 |
| 6121139 | Ti-rich TiN insertion layer for suppression of bridging during a salicide procedure | Shou-Zen Chang | 2000-09-19 |
| 6037204 | Silicon and arsenic double implanted pre-amorphization process for salicide technology | Shou-Zen Chang, Chin-Hsiung Ho, Cheng-Kun Lin | 2000-03-14 |
| 6030863 | Germanium and arsenic double implanted pre-amorphization process for salicide technology | Shou-Zen Chang, Cheng-Kun Lin, Chi-Ming Yang | 2000-02-29 |
| 6022775 | High effective area capacitor for high density DRAM circuits using silicide agglomeration | Mong-Song Liang | 2000-02-08 |
| 5895257 | LOCOS field oxide and field oxide process using silicon nitride spacers | Yuan-Chang Huang, Juing-Yi Wu, Shun-Liang Hsu | 1999-04-20 |
| 5821153 | Method to reduce field oxide loss from etches | Chin-Hsiung Ho | 1998-10-13 |
| 5757045 | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation | Shun-Liang Hsu | 1998-05-26 |
| 5702972 | Method of fabricating MOSFET devices | Shun-Liang Hsu, Shaulin Shue | 1997-12-30 |
| 5691212 | MOS device structure and integration method | Shun-Liang Hsu | 1997-11-25 |
| 5674775 | Isolation trench with a rounded top edge using an etch buffer layer | Chin-Hsiung Ho, Chia-Shiung Tsai, Cheng-Kai Liu | 1997-10-07 |