Issued Patents All Time
Showing 1–25 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11069806 | Integrated circuit including a low-noise amplifying circuit with asymmetrical source and drain regions and a logic circuit with symmetrical source and drain regions | Chuan-Chen Chao, Shu-Yuan Hsu | 2021-07-20 |
| 10992268 | Radio frequency amplification device capable of detecting the frequency band | Cheng-Min Lin | 2021-04-27 |
| 9052332 | Piezoresistive type Z-axis accelerometer | Chih-Wei Huang, Chieh-Pin Chang, Ja-Hao Chen, Chuan-Jane Chao, Ying-Zong Juang +1 more | 2015-06-09 |
| 8904868 | Sensing apparatus | Chih-Wei Huang, Chieh-Pin Chang, Ja-Hao Chen, Chuan-Jane Chao, Ying-Zong Juang +1 more | 2014-12-09 |
| 8265171 | Error resilient video transmission using instantaneous receiver feedback and channel quality adaptive packet retransmission | Eckehard Steinbach, Wei Deng | 2012-09-11 |
| 8026767 | Adaptive bias circuit and system thereof | Chih-Wei Chen, Chuan-Jane Chao | 2011-09-27 |
| 7692493 | High-efficiency single to differential amplifier | Chih-Wei Chen, Chuan-Jane Chao | 2010-04-06 |
| 7693503 | Mixer having filtering module to filter out low-frequency components to minimize noise | Jiong-Guang Su | 2010-04-06 |
| 7437131 | Active mixer with self-adaptive bias feedback | Ching-Kuo Wu, Chih-Wei Chen, YUN-SHAN CHANG | 2008-10-14 |
| 7358817 | Linearized bias circuit with adaptation | Chi-Hung Kao, Chih-Wei Chen, Cheng-Min Lin, YUN-SHAN CHANG | 2008-04-15 |
| 7205844 | Low noise and high gain low noise amplifier | Jiong-Guang Su, Tsyr-Shyang Liou | 2007-04-17 |
| 7193475 | Single-ended input to differential output low noise amplifier with a cascode topology | Jiong-Guang Su, Tsyr-Shyang Liou | 2007-03-20 |
| 7061056 | High fMAX deep submicron MOSFET | Chao-Chieh Tsai, Chung-Long Chang | 2006-06-13 |
| 7030728 | Layout and method to improve mixed-mode resistor performance | Kong-Beng Thei, Chih-Hsien Lin | 2006-04-18 |
| 6943063 | RF seal ring structure | Chaochieh Tsai | 2005-09-13 |
| 6845347 | Method for modeling an integrated circuit including a DRAM cell | Shih-Hsien Yang | 2005-01-18 |
| 6737310 | Self-aligned process for a stacked gate RF MOSFET device | Chaochieh Tsai, Chung-Long Chang, Jui-Yu Chang | 2004-05-18 |
| 6732422 | Method of forming resistors | Kong-Beng Thei, Chih-Hsien Lin | 2004-05-11 |
| RE38319 | Dual-node capacitor coupled MOSFET for improving ESD performance | Shin-Tron Lin | 2003-11-18 |
| 6636139 | Structure to reduce the degradation of the Q value of an inductor caused by via resistance | Chaochieh Tsai | 2003-10-21 |
| 6613623 | High fMAX deep submicron MOSFET | Chao-Chieh Tsai, Chung-Long Chang | 2003-09-02 |
| 6559493 | High density stacked mim capacitor structure | Tzyh-Cheang Lee, Chih-Hsien Lin, Chi-Feng Huang | 2003-05-06 |
| 6501137 | Electrostatic discharge protection circuit triggered by PNP bipolar action | Ta-Lee Yu | 2002-12-31 |
| 6480414 | Multi-level memory cell | Hong-Chin Lin, Tai-Yuan Chen | 2002-11-12 |
| 6476451 | Buried guard rings for CMOS device | — | 2002-11-05 |