TL

Tsyr-Shyang Liou

RT Richwave Technology: 10 patents #7 of 136Top 6%
TSMC: 3 patents #5,465 of 12,232Top 45%
IT ITRI: 1 patents #5,197 of 9,619Top 55%
Overall (All Time): #341,647 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDate
11646712 Bulk acoustic wave structure and bulk acoustic wave device 2023-05-09
11362637 Bulk acoustic wave structure, bulk acoustic wave device, and manufacturing method thereof 2022-06-14
10923365 Connection structure and method for forming the same Chia-Yun Wu, Yu-Ling Chiu 2021-02-16
RE46540 Method and apparatus for integrating a surface acoustic wave filter and a transceiver Yu-Ling Chiu 2017-09-05
8580627 Compound semiconductor device and method for fabricating the same Kuo-Jui Peng, Chuan-Jane Chao 2013-11-12
8129805 Microelectromechanical system (MEMS) device and methods for fabricating the same 2012-03-06
7460851 Method and apparatus for integrating a surface acoustic wave filter and a transceiver Yu-Ling Chiu 2008-12-02
7375590 Single-ended input to differential-ended output low noise amplifier implemented with cascode and cascade topology Jiong-Guang Su, Ja-Hao Chen, Chih-Wei Chen, Shao-Hua Chen, Han Wu 2008-05-20
7372102 Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology Kuan-Lun Chang, Ruey-Hsin Liu, Chih-Min Chiang, Jun-Lin Tsai 2008-05-13
7250344 Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology Kuan-Lun Chang, Ruey-Hsin Liu, Chih-Min Chiang, Jun-Lin Tsai 2007-07-31
7205844 Low noise and high gain low noise amplifier Jiong-Guang Su, Shyh-Chyi Wong 2007-04-17
7193475 Single-ended input to differential output low noise amplifier with a cascode topology Jiong-Guang Su, Shyh-Chyi Wong 2007-03-20
7015086 Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology Kuan-Lun Chang, Ruey-Hsin Liu, Chih-Min Chiang, Jun-Lin Tsai 2006-03-21
6180478 Fabrication process for a single polysilicon layer, bipolar junction transistor featuring reduced junction capacitance Chwan-Ying Lee, Tzuen-Hsi Huang 2001-01-30